參數(shù)資料
型號(hào)： T9000
英文描述： ISDN Network Termination Node (NTN) Device
中文描述： ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)（新界北）設(shè)備
文件頁數(shù)： 63/126頁
文件大?。?/td> 2127K
代理商： T9000
Lucent Technologies Inc.
63
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
T9000
9 HDLC with FIFO Module
(continued)
9.5 HDLC Register Set
(continued)
Table 65. HSM0: HDLC SAPI Match Pattern 0 (0x22)
Table 66. HTM0: HDLC TEI Match Pattern 0 (0x23)
Table 67. HSM1: HDLC SAPI Match Pattern 1 (0x24)
Reg
HSM0
R/W
R/W
Bit 7
SAPI05
BAP7
—
Bit 6
SAPI04
BAP6
—
Bit 5
SAPI03
BAP5
—
Bit 4
SAPI02
BAP4
—
Bit 3
SAPI01
BAP3
—
Bit 2
SAPI00
BAP2
—
Bit 1
C/R0
BAP1
—
Bit 0
EA00
BAP0
—
RESET
Default
Bit #
7—2
Symbol
SAPI0[5:0]
Name/Description
Match Pattern 0 for SAPI.
When in the HDLC mode, this register provides the match
pattern for SAPI. See Section 9.4, Address Recognition for details.
Byte Alignment Pattern
. When in transparent mode, this register provides the byte
alignment pattern if HRCF[BAE] = 1.
Command/Response Bit.
Set according to the Q.920 standard.
Byte Alignment Pattern
. When in transparent mode, this register provides the byte
alignment pattern if HRCF[BAE] = 1.
Address Field Extension Bit (0 or 1).
This bit has to be 0 for recognizing SAPI0 and
SAPI63 addresses.
Byte Alignment Pattern
. When in transparent mode, this register provides the byte
alignment pattern if HRCF[BAE] = 1.
BAP[7:2]
1
C/R0
BAP1
0
EA00
BAP0
Reg
HTM0
RESET
R/W
R/W
Default
Bit 7
TEI06
—
Bit 6
TEI05
—
Bit 5
TEI04
—
Bit 4
TEI03
—
Bit 3
TEI02
—
Bit 2
TEI01
—
Bit 1
TEI00
—
Bit 0
EA10
—
Bit #
7—1
0
Symbol
TEI0[6:0]
EA10
Name/Description
Match Pattern 0 for TEI.
See Section 9.4, Address Recognition for details.
Address Field Extension Bit (0 or 1).
This bit has to be 1 for recognizing the special TEI127
value of 127.
Reg
HSM1
RESET
R/W
R/W
Default
Bit 7
SAPI15
—
Bit 6
SAPI14
—
Bit 5
SAPI13
—
Bit 4
SAPI12
—
Bit 3
SAPI11
—
Bit 2
SAPI10
—
Bit 1
C/R1
—
Bit 0
EA01
—
Bit #
7—2
Symbol
SAPI1[5:0]
Name/Description
Match Pattern 1 for SAPI.
When in the HDLC mode, this register provides the match pat-
tern for SAPI. See Section 9.4, Address Recognition for details.
Command/Response Bit.
Set according to the Q.920 standard.
Address Field Extension Bit (0 or 1).
This bit has to be 0 for recognizing SAPI0 and
SAPI63 addresses.
1
0
C/R1
EA01
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