參數(shù)資料
型號： T9000
英文描述： ISDN Network Termination Node (NTN) Device
中文描述： ISDN網(wǎng)絡(luò)終端節(jié)點（新界北）設(shè)備
文件頁數(shù)： 46/126頁
文件大小： 2127K
代理商： T9000
46
Lucent Technologies Inc.
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
T9000
7 Transmission Superblock
(continued)
7.6 DFAC Register Set
(continued)
Table 39. SIR: S-Interface Interrupt Register (0x16)
Note:
All defined bits in this register are set to 1 upon occurrence of the corresponding interrupt condition, and are
cleared to 0 when the register is read.
Table 40. SIE: S-Interface Interrupt Enable Register (0x17)
This register contains enable bits for the interrupts in register SIR.
Reg
SIR
RESET
R/W
R
Default
Bit 7
—
—
Bit 6
—
—
Bit 5
—
—
Bit 4
—
—
Bit 3
SSC
0
Bit 2
FSERRL
0
Bit 1
QSC
0
Bit 0
SSRDY
0
Bit #
7—4
3
Symbol
—
SSC
Name/Description
Reserved.
S-Interface Activation State Change.
This interrupt occurs whenever any one of the
RXINFO3, RXINFO1, and ASI[2:0] bits in register SSR changes state.
S-Interface Receiver Frame Synchronization Error, Latched.
This interrupt occurs on the
rising edge of the FSERR signal from the S block (see bit SSR[FSERR]), and is reset when
read. Note that this interrupt will occur only when FSERR transitions from 0 to 1. If the FSERR
condition persists after reading this bit, it will not cause this bit to be set again until FSERR
goes away, and then transitions to 1 again. To poll the current state of FSERR, bit
SSR[FSERR] can be used.
S-Interface Q Bit Change.
This interrupt occurs to signal that a complete Q-channel nibble
has been received and is available in register MFR0.
S-Interface Ready to Accept New S-Channel Nibble.
This interrupt occurs to signal that the
current S-subchannel nibbles have been transmitted and a new set may be written to register
MFR1.
2
FSERRL
1
QSC
0
SSRDY
Reg
SIE
RESET
R/W
R/W
Default
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
SSCE
0
Bit 2
Bit 1
QSCE
0
Bit 0
SSRDYE
0
FSERRLE
0
Bit #
7—4
3
Symbol
—
SSCE
Name/Description
Reserved.
Program to 0.
SSC Interrupt Enable.
0: Interrupt disabled.
1: Interrupt enabled.
2
FSERRLE
FSERRL Interrupt Enable.
0: Interrupt disabled.
1: Interrupt enabled.
QSC Interrupt Enable.
1
QSCE
0: Interrupt disabled.
1: Interrupt enabled.
SSRDY Interrupt Enable.
0
SSRDYE
0: Interrupt disabled.
1: Interrupt enabled.
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