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參數(shù)資料
| 型號： | T9000 |
| 英文描述： | ISDN Network Termination Node (NTN) Device |
| 中文描述： | ISDN網(wǎng)絡(luò)終端節(jié)點（新界北）設(shè)備 |
| 文件頁數(shù)： | 34/126頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | T9000 |
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34
Lucent Technologies Inc.
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
T9000
7 Transmission Superblock
(continued)
7.6 DFAC Register Set
(continued)
Table 23. DFR: Data Flow Register (0x06)
Reg
DFR
RESET
R/W
R/W
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
B2_SEL B1_SEL BSWAP
0
0
Bit 1
Bit 0
U_FORCE_B2UP
0
U_FORCE_B1UP FORCE_D
0
PFS2_ACT
0
PFS1_ACT
0
0
0
Bit #
7
Symbol
Name/Description
U_FORCE_B2UP
Microcontroller Access to Upstream B2 Channel.
When this bit is set, the microcontroller can
access the upstream B2-channel data from the GCI to the U-interface via the register B2UP (0x52)
assuming that DFR[B2_SEL] = 1 and ECR0[LB2] = 0.
Microcontroller Access to Upstream B1 Channel.
When this bit is set, the microcontroller can
access the upstream B1-channel data from the GCI to the U-interface via the register B1UP (0x51)
assuming that DFR[B1_SEL] = 1 and ECR0[LB1] = 0.
Force Local D-Channel Access.
When this bit is asserted, D-channel arbitration is disabled
and upstream access to the D channel is granted exclusively to the local HDLC controller.
0: Normal operation. Upstream D-channel arbitration is automatically provided (with an
equal priority) between the local HDLC controller and the upstream D channel from the
S/T-interface.
1: Upstream D-channel access is granted exclusively to the HDLC controller.
6
U_FORCE_B1UP
5
FORCE_D
4
PFS2_ACT
Programmable Frame Strobe-2 Output Enable on GCI+ Interface.
See Section 10, GCI+ Inter-
face Module for detailed information.
0: Function PFS2 is disabled. FS2 output drives a zero level. Data downstream (DD) pin is
3-stated during the corresponding time slot.
1: PFS2 is enabled.
Programmable Frame Strobe-1 Output Enable on GCI+ Interface.
See GCI+ section for detailed
information.
0: Function PFS1 is disabled. In TDM mode, FS1 output drives a zero level. In GCI mode,
GPIO2.2 drives a zero level (assuming GPAF1[GPAF2.2] = 1). Data downstream (DD) pin
is 3-stated during the corresponding time slot.
1: PFS1 is enabled and will be output on pin FS1 (in TDM mode) or GPIO2.2 (in GCI mode,
assuming GPAF1[GPAF2.2] = 1).
3
PFS1_ACT
2
B2_SEL
U-Interface B2-Channel Source/Destination.
0: U-interface B2 channel to/from S/T-interface.
1: U-interface B2 channel to/from GCI+ interface (or microcontroller if U_FORCE_B2UP is set).
U-Interface B1-Channel Source/Destination.
1
B1_SEL
0: U-interface B1 channel to/from S/T-interface.
1: U-interface B1 channel to/from GCI+ interface (or microcontroller if U_FORCE_B1UP is set).
B-Channel Swap on GCI+ Interface.
No effect on device operation unless either B1_SEL = 1
or B2_SEL = 1. See GCI+ interface section for details on the assignment of B channels to GCI+
time slots.
0: Normal operation.
1: When B1_SEL = 1, the U-interface B1 channel source/destination is the channel on which
the B2 channel is assigned on the GCI+ interface. When B2_SEL = 1, the U-interface
B2-channel source/destination is the channel on which the B1 channel is assigned on
the GCI+ interface.
0
BSWAP
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