參數(shù)資料
型號： T9000
英文描述： ISDN Network Termination Node (NTN) Device
中文描述： ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)（新界北）設(shè)備
文件頁數(shù)： 64/126頁
文件大?。?/td> 2127K
代理商： T9000
64
Lucent Technologies Inc.
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
T9000
9 HDLC with FIFO Module
(continued)
9.5 HDLC Register Set
(continued)
Table 68. HTM1: HDLC TEI Match Pattern 1 (0x25)
Table 69. HSM2: HDLC SAPI Match Pattern 2 (0x26)
Table 70. HTM2: HDLC TEI Match Pattern 2 (0x27)
Table 71. HSM3: HDLC SAPI Match Pattern 3 (0x28)
Reg
HTM1
RESET
R/W
R/W
Default
Bit 7
TEI16
—
Bit 6
TEI15
—
Bit 5
TEI14
—
Bit 4
TEI13
—
Bit 3
TEI12
—
Bit 2
TEI11
—
Bit 1
TEI10
—
Bit 0
EA11
—
Bit #
7—1
0
Symbol
TEI1[6:0]
Match Pattern 1 for TEI.
See Section 9.4, Address Recognition for details.
EA11
Address Field Extension Bit (0 or 1).
This bit has to be 1 for recognizing the special TEI value
of 127.
Name/Description
Reg
HSM2
RESET
R/W
R/W
Default
Bit 7
SAPI25
—
Bit 6
SAPI24
—
Bit 5
SAPI23
—
Bit 4
SAPI22
—
Bit 3
SAPI21
—
Bit 2
SAPI20
—
Bit 1
C/R2
—
Bit 0
EA02
—
Bit #
7—2
Symbol
SAPI2[5:0]
Name/Description
Match Pattern 2 for SAPI.
When in the HDLC mode, this register provides the match
pattern for SAPI. See Section 9.4, Address Recognition for details.
Command/Response Bit.
Set according to the Q.920 standard.
Address Field Extension Bit (0 or 1).
This bit has to be 0 for recognizing special SAPI
values of 0 or 63.
1
0
C/R2
EA02
Reg
HTM2
RESET
R/W
R/W
Default
Bit 7
TEI26
—
Bit 6
TEI25
—
Bit 5
TEI24
—
Bit 4
TEI23
—
Bit 3
TEI22
—
Bit 2
TEI21
—
Bit 1
TEI20
—
Bit 0
EA12
—
Bit #
7—1
0
Symbol
TEI2[6:0]
Match Pattern 2 for TEI.
See Section 9.4, Address Recognition for details.
EA12
Address Field Extension Bit (0 or 1).
This bit has to be 1 for recognizing the special TEI
value of 127.
Name/Description
Reg
HSM3
RESET
R/W
R/W
Default
Bit 7
SAPI35
—
Bit 6
SAPI34
—
Bit 5
SAPI33
—
Bit 4
SAPI32
—
Bit 3
SAPI31
—
Bit 2
SAPI30
—
Bit 1
C/R3
—
Bit 0
EA03
—
Bit #
7—2
Symbol
SAPI3[5:0]
Name/Description
Match Pattern 3 for SAPI.
When in the HDLC mode, this register provides the match
pattern for SAPI. See Section 9.4, Address Recognition for details.
Command/Response Bit.
Set according to the Q.920 standard.
Address Field Extension Bit (0 or 1).
This bit has to be 0 for recognizing special SAPI
values of 0 or 63.
1
0
C/R3
EA03
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