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| 型號(hào)： | T9000 |
| 英文描述： | ISDN Network Termination Node (NTN) Device |
| 中文描述： | ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)（新界北）設(shè)備 |
| 文件頁(yè)數(shù)： | 91/126頁(yè) |
| 文件大小： | 2127K |
| 代理商： | T9000 |
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Lucent Technologies Inc.
91
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
T9000
11 GPIO Ports
(continued)
11.1 GPIO Register Set
(continued)
Table 99. GPPOL: GPIO Interrupt Polarity Control (0x41)
Table 100
.
GPIR: GPIO Interrupt Register (0x42)
Note:
All bits in this register are set to 1 upon occurrence of the corresponding interrupt condition and are cleared
to 0 when the register is read, except in level-triggering mode. When in level-triggering mode, this register is
cleared when read only if the source of the interrupt has been taken away. They are also cleared upon writ-
ing a one to the corresponding bits in GPPOL registers.
Reg
GPPOL
RESET
R/W
R/W
Default
Bit 7
IPOL1.3
1
Bit 6
IPOL1.2
1
Bit 5
IPOL1.1
1
Bit 4
IPOL1.0
1
Bit 3
IPOL0.3
1
Bit 2
IPOL0.2
1
Bit 1
IPOL0.1
1
Bit 0
IPOL0.0
1
Bit #
7—4
Symbol
IPOL1.[3:0]
Name/Description
Interrupt Polarity for GPIO1.[3:0] Pins.
Only applicable when pin is an input (see regis-
ter GPDIR1). IPOL1.x specifies value of GPIO1.x that generates an interrupt.
0: Level-triggered => Interrupt when level is 0.
Edge-triggered => Interrupt on falling edge.
1: Level-triggered => Interrupt when level is 1.
Edge-triggered => Interrupt on rising edge.
Interrupt Polarity for GPIO0.[3:0] Pins.
Only applicable when pin is an input (see regis-
ter GPDIR0). IPOL0.x specifies value of GPIO0.x that generates an interrupt.
3—0
IPOL0.[3:0]
0: Level-triggered => Interrupt when level is 0.
Edge-triggered => Interrupt on falling edge.
1: Level-triggered => Interrupt when level is 1.
Edge-triggered => Interrupt on rising edge.
Reg
GPIR
RESET
R/W
R/W
Default
Bit 7
GPI1.3
—
Bit 6
GPI1.2
—
Bit 5
GPI1.1
—
Bit 4
GPI1.0
—
Bit 3
GPI0.3
—
Bit 2
GPI0.2
—
Bit 1
GPI0.1
—
Bit 0
GPI0.0
—
Bit #
7—4
Symbol
GPIx.[3:0]
Name/Description
GPIO1.x Interrupt.
This interrupt occurs when the appropriate edge or level, as deter-
mined by the GPLEI and GPPOL registers, has been sensed on the corresponding GPIO
pin.
GPIO0.x Interrupt.
This interrupt occurs when the appropriate edge or level, as deter-
mined by the GPLEI and GPPOL registers, has been sensed on the corresponding GPIO
pin.
3—0
GPIx.[3:0]
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