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參數(shù)資料
| 型號： | T9000 |
| 英文描述： | ISDN Network Termination Node (NTN) Device |
| 中文描述： | ISDN網(wǎng)絡終端節(jié)點（新界北）設(shè)備 |
| 文件頁數(shù)： | 60/126頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | T9000 |
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60
Lucent Technologies Inc.
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
T9000
9 HDLC with FIFO Module
(continued)
9.5 HDLC Register Set
(continued)
Table 57. HTTH: HDLC Transmit FIFO Threshold (0x1A)
Table 58. HRTH: HDLC Receive FIFO Threshold (0x1B)
Reg
HTTH
RESET
R/W
R/W
Default
Bit 7
Bit 6
—
0
Bit 5
TFAE5
1
Bit 4
TFAE4
0
Bit 3
TFAE3
0
Bit 2
TFAE2
0
Bit 1
TFAE1
0
Bit 0
TFAE0
0
P_CLASS
1
Bit #
7
Symbol
P_CLASS
Priority Class
. This bit is used during arbitration to the upstream D-channel access. It indi-
cates the number of consecutive ones the NTN has to receive on the upstream S/T D chan-
nel in order to grant D-channel access to the HDLC transmitter.
Name/Description
0: Priority class 2 (data) as defined in ITU-I.430.
1: Priority class 1 (signaling) as defined in ITU-I.430.
Within a class, priority levels are automatically managed.
Reserved.
Program to 0.
TFAE[5:0]
HDLC Transmitter FIFO Almost Empty Threshold.
The HDLC transmitter will issue an
interrupt (if enabled) when the number of empty bytes in the transmit FIFO exceeds the
threshold level programmed in this register. The interrupt will clear when the interrupt status
register is read. The interrupt will not be asserted again until the number of empty bytes in the
transmit FIFO is equal to or less than the value programmed in TFAE[5:0], and then enough
bytes are transmitted to again cause the FIFO empty level to exceed the TFAE[5:0] value.
6
—
5—0
Reg
HRTH
RESET
R/W
R/W
Default
Bit 7
—
0
Bit 6
—
0
Bit 5
RFAF5
1
Bit 4
RFAF4
0
Bit 3
RFAF3
0
Bit 2
RFAF2
0
Bit 1
RFAF1
0
Bit 0
RFAF0
0
Bit #
7—6
5—0
Symbol
—
Name/Description
Reserved.
Program to 0.
HDLC Receiver FIFO Almost Full Threshold.
The HDLC receiver will issue an interrupt
(if enabled) when the number of bytes in the receive FIFO exceeds the threshold level
programmed in this register. The interrupt will clear when the interrupt status register is
read. The interrupt will not be asserted again until the number of bytes in the receive
FIFO is equal to or less than the value programmed in RFAF[5:0], and enough bytes are
received to again cause the FIFO fill level to exceed the RFAF[5:0] value.
RFAF[5:0]
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