參數(shù)資料
型號(hào): TMPR4955
廠商: Toshiba Corporation
英文描述: 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器)
中文描述: 64位RISC(精簡指令集計(jì)算機(jī))微處理器(64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器)
文件頁數(shù): 33/60頁
文件大小: 244K
代理商: TMPR4955
TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
33
5.7.7
External arbitration protocol
As previously mentioned, the ExtRqst* signal and Release* signal are used in system interface arbitration.
Figure 7-7 illustrates the timing of the arbitration protocol when the slave state changes to the master
state.
The arbitration cycle sequence is as follows.
1.
The external agent asserts ExtRqst* when it becomes necessary to issue external requests.
2.
The processor asserts Release* for 1 cycle when it becomes possible to process an external request.
3.
The processor sets the SysAD bus and SysCmd bus to tri-state.
4.
The external agent must start transmission to the SysAD bus and SysCmd bus 2 cycles after Release*
is asserted.
5.
The external agent deasserts ExtRqst* 2 cycles after Release* is asserted. This does not apply
however to situations where an attempt is made to issue another external request.
6.
The external agent sets the SysAD bus and SysCmd bus to tri-state when processing of the external
request is complete.
The processor becomes able to issue processor requests 1 cycle after the external agent sets the busses to
tri-state.
Note:
The SysADC bus and SysCmdP bus timing is the same as that for the SysAD bus and SysCmd
bus, respectively.
Figure 7-7 Arbitration Protocol Relating to External Requests
3
4
6
Master
Clock
Cycle
SysAD bus
SysCmd bus
ValidIn*
Master
Slave
Master
1
2
3
4
5
6
7
8
9
10
11
12
Addr
Data0
Cmd
NEOD
1
2
5
ExtRqst*
Release*
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