參數(shù)資料
型號: TMPR4955
廠商: Toshiba Corporation
英文描述: 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器)
中文描述: 64位RISC(精簡指令集計算機)微處理器(64位精簡指令集系統(tǒng)計算機微處理器)
文件頁數(shù): 39/60頁
文件大?。?/td> 244K
代理商: TMPR4955
TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
39
5.8 Data Transfer
The maximum data transfer rate of the system interface is 1 double word per cycle.
The external agent can select the data transfer rate to the processor. For example, it is possible to transfer
data and assert the ValidIn* signal just once for every
n
cycles instead of at all cycles. The external agent
can transfer data to the processor at the selected transfer rate.
The processor interprets cycles as being valid when the ValidIn* signal is asserted and the SysCmd bus
includes the data identifier. After a cycle has been interpreted as valid, the processor continues to accept
data until a data word with an indication that it is the final data word appears.
5.8.1 Data transfer pattern
The term “data pattern” in the case of block write operations, refers to a string of text that indicates the
“data” cycles repeated so that the appropriate data transfer speed can be obtained and the “unused” cycles.
Dxx data patterns indicate a repetition data transfer rate where there is one double word in three cycles
followed by two unused cycles. The data transfer rate is set by G2Sconfig register(0xF FF10 0000).
Table 8-1 indicates the data transfer rate, data pattern, and setting.
Maximum Data Transfer Rate
Data Pattern
Setting
Bit(2:1)
00
01
10
11
Write mode
1 double word/3 Master Clock cycle
Reserved
1 double word/1 Master Clock cycles
1 double word/1 Master Clock cycles
Dxx
R4000 compatible
Reserved
Pipeline write
Reissue write
Reserved
D
D
Note:
Bit(2:1) is set to “00” when initialized.
The setting Bit(2:1) is bit(2:1) of the G2Sconfig register (0xF FF10 0000).
Table 8-1 Data Transfer Rate, Data Pattern and Setting
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