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| 型號： | TMPR4955 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機）微處理器（64位精簡指令集系統(tǒng)計算機微處理器） |
| 文件頁數： | 36/60頁 |
| 文件大小： | 244K |
| 代理商： | TMPR4955 |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
36
5.7.10 External write request protocol
The same protocol as the processor single word write protocol is used for external write requests, except
when the ValidIn* signal is asserted instead of the ValidOut* signal.
Figure 7-10 illustrates the timing of the external write request, which consists of the following steps.
1.
The external agent requests use of the system interface by asserting ExtRqst*.
2.
The processor asserts Release*, then the system interface is released from the processor and goes into
the slave state.
3.
The external agent sends a write command to the SysCmd bus, and sends a write address to the
SysAD bus while asserting ValidIn*.
4.
The external agent sends data identifiers to the SysCmd bus, and sends data to the SysAD bus while
asserting ValidIn*.
5.
Data identifiers for this data cycle must contain an indication of a coherent or non-coherent final data
cycle.
6.
After a data cycle is issued, the write request is complete, the external agent sets the SysCmd and
SysAD busses to tri-state, then the system interface returns to the master state. Timing of the
SysADC bus and SysCmdP bus are each the same as the SysAD bus and SysCmd bus, respectively.
External write requests can write only 1 word of data to the processor. Operation of processors that have
specified data elements other than a single word of data by an external write request is not defined.
Figure 7-10 External Write Request when System Interface Starts in the Master State
Master
Clock
SysAD bus
Cycle
SysCmd bus
ValidOut*
ValidIn*
ExtRqst*
Release*
Master
Slave
Master
1
2
3
4
5
6
7
8
9
10
11
12
Addr
Data0
Write
NEOD
1
2
3
4
5
4
6
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TMPR4955A | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
| TMPR4955AF | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
| TMPR4955AF-167 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| TMPR4955AF-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|64-BIT|CMOS|QFP|160PIN|PLASTIC |
| TMPR4955B | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:64-Bit TX System RISC TX49 Family |
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