參數(shù)資料
型號: TMPR4955
廠商: Toshiba Corporation
英文描述: 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器)
中文描述: 64位RISC(精簡指令集計算機)微處理器(64位精簡指令集系統(tǒng)計算機微處理器)
文件頁數(shù): 45/60頁
文件大小: 244K
代理商: TMPR4955
TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
45
5.10.5 Null requests
Figure 10-4 illustrates the SysCmd format for null requests.
0
0 1 1
Figure 10-4 Bit Definition of the SysCmd Bus for Null Requests
Null request commands are always used for system interface release external null requests. Table 10-8
indicates methods of specifying SysCmd(4:3) for system interface release external null requests.
SysCmd(2:0) is reserved for null requests.
SysCmd(4:3)
0
1 – 3
Null Properties
Release system interface
Reserved
Table 10-8 Method of Specifying SysCmd(4:3) for External Null Requests
5.10.6 Syntax of system interface data identifiers
This section defines methods of specifying the SysCmd bus for system interface identifiers. The bit
structure illustrated in Figure 10-5 is common to all system interface data identifiers.
Figure 10-5 Bit Definition of SysCmd Bus for Data Identifiers
SysCmd(8) must always be set to “1” for system interface data identifiers. System interface data
identifiers are in the non-coherent data format.
5.10.7
Non-coherent data
Non-coherent data are data such as the following.
Data that are the subject of a processor block write request or a processor double word/partial
double word/word/partial word write request.
Data that are returned to a processor non-coherent block read request or a processor double word/
partial double word/word/partial word read request.
Data that are the subject of an external write request.
Data that are returned to an external read request as a response.
8
7
5
4
0
Null request specific
8
Final
Data
Response
Data
Error
Data
Reserved
1
7
6
5
4
3
0
Data
Check
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