參數(shù)資料
型號: TMS320VC5409GGU-80
廠商: Texas Instruments
文件頁數(shù): 29/93頁
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-BGA
標準包裝: 160
系列: TMS320C54x
類型: 定點
接口: 主機接口,McBSP
時鐘速率: 80MHz
非易失內存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應商設備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Functional Overview
35
April 1999 Revised October 2008
SPRS082F
3.3.2.1
Sample Rate Generator
The 5409 sample rate generator has four clock input options that are only available when both the PCR and
SRGR2 are used. Table 38 shows the sample rate generator clock input options.
Table 38. Sample Rate Generator Clock Input Options
MODE
SCLKME
(PCR.7)
CLKSM
(SRGR2.13)
CLKS pin
0
CPU
0
1
CLKR pin
1
0
CLKX pin
1
15
14
13
12
11
8
GSYNC
CLKSP
CLKSM
FSGM
FPER
R/W-0
R/W
7
0
FPER
R/W
LEGEND: R = Read, W = Write, n = value present after reset
Figure 39. Sample Rate Generator Register 2 (SRGR2)
Table 39. Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions
BIT
NAME
FUNCTION
BIT
NAME
FUNCTION
15
GSYNC
Sample rate generator clock synchronization. Only used when the external clock (CLKS) drives the sample rate
generator clock (CLKSM=0)
GSYNC = 0
The sample rate generator clock (CLKG) is free-running.
GSYNC = 1
The sample rate generator clock (CLKG) is running. But CLKG is resynchronized and frame sync
signal (FSG) is generated only after detecting the receive frame synchronization signal (FSR). Also,
frame period (FPER) is a don’t care because the period is dictated by the external frame sync pulse.
14
CLKSP
CLKS polarity clock edge select. Only used when the external clock (CLKS) drives the sample rate generator clock
(CLKSM=0).
CLKSP = 0
Rising edge of CLKS generates CLKG and FSG.
CLKSP = 1
Falling edge of CLKS generates CLKG and FSG.
13
CLKSM
McBSP sample rate generator clock mode
SCLKME = 0
CLKSM = 0
Sample rate generator clock derived from the CLKS pin
(in PCR)
CLKSM = 1
Sample rate generator clock derived from CPU clock
SCLKME = 1
CLKSM = 0
Sample rate generator clock derived from CLKR pin
(in PCR)
CLKSM = 1
Sample rate generator clock derived from CLKX pin
12
FSGM
Sample rate generator transmit frame synchronization mode. Used when FSXM=1 in the PCR.
FSGM = 0
Transmit frame sync signal (FSX) due to DXR(1/2) copy
FSGN = 1
Transmit frame sync signal driven by the sample rate generator frame sync signal (FSG)
11 0
FPER
Frame period. This determines when the next frame sycn signal should become active. Range: up to 212;
1 to 4096 CLKG periods.
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