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| 型號： | TMS320VC5409GGU-80 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 8/93頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIXED POINT DSP 144-BGA |
| 標準包裝： | 160 |
| 系列： | TMS320C54x |
| 類型： | 定點 |
| 接口： | 主機接口，McBSP |
| 時鐘速率： | 80MHz |
| 非易失內(nèi)存： | ROM（32 kB） |
| 芯片上RAM： | 64kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LFBGA |
| 供應商設備封裝： | 144-BGA MICROSTAR（12x12） |
| 包裝： | 托盤 |
| 配用： | 296-15829-ND - DSP STARTER KIT FOR TMS320C5416 |
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Introduction
16
April 1999 Revised October 2008
SPRS082F
Table 22. Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
I/O
INTERNAL
TERMINAL
NAME
DESCRIPTION
I/O
PIN STATE
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter
is fetching the interrupt vector location designated by A15A0. IACK also goes into the
high-impedance state when OFF is low.
INT0
INT1
INT2
INT3
Schmitt
trigger
I
External user interrupts. INT0INT3 are prioritized and are maskable by the interrupt mask register
and the interrupt mode bit. INT0 INT3 can be polled and reset by way of the interrupt flag register.
NMI
Schmitt
trigger
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or
the IMR. When NMI is activated, the processor traps to the appropriate vector location.
RS
Schmitt
trigger
I
Reset. RS causes the DSP to terminate execution and causes a reinitialization of the CPU and
peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
MP/MC
I
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is
selected, and the internal program ROM is mapped into the upper program memory space. If the
pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed
from program space. MP/MC is only sampled at reset, and the MP/MC bit of the PMST register can
override the mode that is selected at reset.
MULTIPROCESSING SIGNALS
BIO
Schmitt
trigger
I
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor
executes the conditional instruction. For the XC instruction, the BIO condition is sampled during the
decode phase of the pipeline; all other instructions sample BIO during the read phase of the
pipeline.
XF
O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF
instruction, set low by the RSBX XF instruction or by loading ST1. XF is used for signaling other
processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into
the high-impedance state when OFF is low, and is set high at reset.
MEMORY CONTROL SIGNALS
DS
PS
IS
O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
accessing a particular external memory space. Active period corresponds to valid address
information. DS, PS, and IS are placed into the high-impedance state in the hold mode; the signals
also go into the high-impedance state when OFF is low.
MSTRB
O/Z
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus
access to data or program memory. MSTRB is placed in the high-impedance state in the hold mode;
it also goes into the high-impedance state when OFF is low.
READY
I
Data ready. READY indicates that an external device is prepared for a bus transaction to be
completed. If the device is not ready (READY is low), the processor waits one cycle and checks
READY again. Note that the processor performs ready detection if at least two software wait states
are programmed. The READY signal is not sampled until the completion of the software wait states.
R/W
O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device.
R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write
operation. R/W is placed in the high-impedance state in hold mode; it also goes into the
high-impedance state when OFF is low.
IOSTRB
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus
access to an I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also
goes into the high-impedance state when OFF is low.
HOLD
I
Hold. HOLD is asserted to request control of the address, data, and control lines. When
acknowledged by the C54x, these lines go into the high-impedance state.
I = Input, O = Output, Z = High-impedance, S = Supply
Although this pin includes an internal pulldown resistor, a 470- external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the VIL and VIH specifications are met.
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