Table 512 an" />
參數(shù)資料
型號(hào): TMS320VC5409GGU-80
廠商: Texas Instruments
文件頁(yè)數(shù): 58/93頁(yè)
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-BGA
標(biāo)準(zhǔn)包裝: 160
系列: TMS320C54x
類(lèi)型: 定點(diǎn)
接口: 主機(jī)接口,McBSP
時(shí)鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤(pán)
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Documentation Support
61
April 1999 Revised October 2008
SPRS082F
5.8
Ready Timing for Externally Generated Wait States
Table 512 and Table 513 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 59, Figure 510, Figure 511, and Figure 512).
Table 512. Ready Timing Requirements for Externally Generated Wait States
MIN
MAX
UNIT
tsu(RDY)
Setup time, READY before CLKOUT low
7
ns
th(RDY)
Hold time, READY after CLKOUT low
0
ns
tv(RDY)MSTRB
Valid time, READY after MSTRB low
4H9
ns
th(RDY)MSTRB
Hold time, READY after MSTRB low
4H
ns
tv(RDY)IOSTRB
Valid time, READY after IOSTRB low
5H9
ns
th(RDY)IOSTRB
Hold time, READY after IOSTRB low
5H
ns
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Table 513. Ready Switching Characteristics for Externally Generated Wait States
PARAMETER
MIN
MAX
UNIT
td(MSCL)
Delay time, CLKOUT low to MSC low
0
3
ns
td(MSCH)
Delay time, CLKOUT low to MSC high
0
3
ns
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
MSC
MSTRB
READY
A[22:0]
CLKOUT
tv(MSCH)
tv(MSCL)
th(RDY)
th(RDY)MSTRB
tv(RDY)MSTRB
Wait State
Generated
by READY
Wait States
Generated Internally
tsu(RDY)
NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
Figure 59. Memory Read With Externally Generated Wait States
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