參數(shù)資料
型號: TMS320VC5409GGU-80
廠商: Texas Instruments
文件頁數(shù): 30/93頁
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-BGA
標(biāo)準(zhǔn)包裝: 160
系列: TMS320C54x
類型: 定點
接口: 主機接口,McBSP
時鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Functional Overview
36
April 1999 Revised October 2008
SPRS082F
3.3.2.2
McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The serial port subbank address (SPSA) register is used as a pointer to select a particular register
within the subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected
register. Table 310 shows the McBSP control registers and their corresponding subaddresses.
Table 310. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
McBSP2
SUB
DESCRIPTION
NAME
ADDRESS
NAME
ADDRESS
NAME
ADDRESS
SUB
ADDRESS
DESCRIPTION
SPCR10
39h
SPCR11
49h
SPCR12
35h
00h
Serial port control register 1
SPCR20
39h
SPCR21
49h
SPCR22
35h
01h
Serial port control register 2
RCR10
39h
RCR11
49h
RCR12
35h
02h
Receive control register 1
RCR20
39h
RCR21
49h
RCR22
35h
03h
Receive control register 2
XCR10
39h
XCR11
49h
XCR12
35h
04h
Transmit control register 1
XCR20
39h
XCR21
49h
XCR22
35h
05h
Transmit control register 2
SRGR10
39h
SRGR11
49h
SRGR12
35h
06h
Sample rate generator register 1
SRGR20
39h
SRGR21
49h
SRGR22
35h
07h
Sample rate generator register 2
MCR10
39h
MCR11
49h
MCR12
35h
08h
Multichannel register 1
MCR20
39h
MCR21
49h
MCR22
35h
09h
Multichannel register 2
RCERA0
39h
RCERA1
49h
RCERA2
35h
0Ah
Receive channel enable register
partition A
RCERB0
39h
RCERB1
49h
RCERB2
35h
0Bh
Receive channel enable register
partition B
XCERA0
39h
XCERA1
49h
XCERA2
35h
0Ch
Transmit channel enable register
partition A
XCERB0
39h
XCERB1
49h
XCERB2
35h
0Dh
Transmit channel enable register
partition B
PCR0
39h
PCR1
49h
PCR2
35h
0Eh
Pin control register
3.3.3 Hardware Timer
The 5409 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer is
decremented by one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timer can be stopped, restarted, reset, or disabled by specific control bits.
3.3.4 Clock Generator
The clock generator provides clocks to the 5409 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock
input is then divided by two (DIV mode) to generate clocks for the 5409 device, or the PLL circuit can be used
(PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor,
allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that,
once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5409
device.
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