Documentation Support
83
April 1999 Revised October 2008
SPRS082F
Table 534. HPI16 Mode Switching Characteristics§
PARAMETER
MIN
MAX
UNIT
ten(DSL-HD)
Enable time, Dx driven from DS low
6
19
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) < 18H
18H+19 – tw(DSH)
td(DSL-HDV1)
Delay time, DS low to Dx valid for an
HPI read
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) ≥ 18H
19
ns
td(DSL-HDV1)
Delay time, DS low to Dx valid for an
HPI read
Case 2a: Memory accesses when
DMAC is inactive and tw(DSH) < 10H
10H+19 – tw(DSH)
ns
Case 2b: Memory accesses when
DMAC is inactive and tw(DSH) ≥ 10H
19
Case 3: Register accesses
19
th(DSH-HDV)R
Hold time, Dx valid after DS rising edge, read
1
8
ns
tv(HYH-HDV)
Valid time, Dx valid before HRDY rising edge
0
6
ns
td(DSH-HYL)
Delay time, DS or HCS high to HRDY low
10
ns
td(DSH-HYH)
Delay time, DS high to HRDY high
Case 1: Memory access when DMAC
is active in 16-bit mode
18H+10
ns
td(DSH-HYH)
Delay time, DS high to HRDY high
(writes and autoincrement reads)
Case 2: Memory access when DMAC
is inactive
10H+10
ns
td(DSL-HYL)
Delay time, HDS or HCS low/high to HRDY low/high
10
ns
td(COHHYH)
Delay time, CLKOUT high to HRDY high
2
ns
NOTE: The HRDY output is always high when the HCS input is high, regardless of DS timings.
DS refers to the logical OR of HCS, HDS1, or HDS2.
Dx refers to any of the DPI data bus pins (D0, D1, D2, etc.).
§ DMAC stands for direct memory access (DMA) controller. The HPI16 shares the internal DMA bus with the DMAC, thus HPI16 access times are
affected by DMAC activity.
GPIO refers to the HD pins when they are configured as general-purpose input/outputs.