參數(shù)資料
型號(hào)： TMS320VC5409GGU-80
廠商： Texas Instruments
文件頁(yè)數(shù)： 47/93頁(yè)
文件大?。?/td> 0K
描述： IC FIXED POINT DSP 144-BGA
標(biāo)準(zhǔn)包裝： 160
系列： TMS320C54x
類型： 定點(diǎn)
接口： 主機(jī)接口，McBSP
時(shí)鐘速率： 80MHz
非易失內(nèi)存： ROM（32 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.80V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 144-LFBGA
供應(yīng)商設(shè)備封裝： 144-BGA MICROSTAR（12x12）
包裝： 托盤(pán)
配用： 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Documentation Support
51
April 1999 Revised October 2008
SPRS082F
5.3
Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
IOH = MAX
2.4
V
VOL
Low-level output voltage
IOL = MAX
0.4
V
IIZ
Input
current
for
outputs
in
high
D[15:0], HD[7:0], A[15:0]
Bus holders enabled, DVDD = MAX,
VI = VSS to DVDD
200
A
IIZ
outputs
in
high
impedance
All other inputs
DVDD = MAX, VO = VSS to DVDD
5
A
X2/CLKIN
40
TRST
With internal pulldown
5
200
II
Input current
HPIENA, HPI16
With internal pulldown
(VI = VSS
to DV
)
5
200
A
II
Input current
TMS, TCK, TDI, HPI}
With internal pullups,
HPIENA = 0
(VI = VSS
to DVDD)
200
5
A
All other input-only pins
5
All other input-only pins
5
IDDC
Supply current, core CPU
CVDD = 1.8 V, fclock = 100 MHz,w TC = 25°C
37
mA
IDDP
Supply current, pins
DVDD = 3.3 V, fclock = 100 MHz,w TC = 25°C#
45
mA
IDD
Supply current,
standby
IDLE2
PLL
× 2 mode, 50 MHz input
2
mA
IDD
Supply current,
standby
IDLE3
Divide-by-two mode, CLKIN stopped
20
A
Ci
Input capacitance
5
pF
Co
Output capacitance
5
pF
All values are typical unless otherwise specified.
HPI input signals except for HPIENA.
§ Clock mode: PLL × 1 with external source
This value represents the current consumption of the CPU, on-chip memory, and on-chip peripherals. Conditions include: program execution from
on-chip RAM, with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed.
# This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF=0, full-duplex
operation of all three McBSPs at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this calculation
is performed, refer to the Calculation of TMS320LC54x Power Dissipation Application Report (literature number SPRA164).
The following load circuit in Figure 51 was used on all outputs pins and I/O pins in input mode. All timing
measurements in this data sheet were measured from the 5409 connection to the following load circuit.
Tester Pin
Electronics
VLoad
IOL
CT
IOH
Output
Under
Test
50
Where:
IOL
= 1.5 mA (all outputs)
IOH
= 300
A (all outputs)
VLoad = 1.5 V
CT
= 40-pF typical load circuit capacitance
Figure 51. 3.3-V Test Load Circuit
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