參數(shù)資料
型號(hào): TMS320VC5409GGU-80
廠商: Texas Instruments
文件頁(yè)數(shù): 37/93頁(yè)
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-BGA
標(biāo)準(zhǔn)包裝: 160
系列: TMS320C54x
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP
時(shí)鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤(pán)
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Functional Overview
42
April 1999 Revised October 2008
SPRS082F
3.3.5.10 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available
modes are shown in Table 312.
Table 312. DMA Interrupts
MODE
DINM
IMOD
INTERRUPT
ABU (non-decrement)
1
0
At full buffer only
ABU (non-decrement)
1
At half buffer and full buffer
Multi-Frame
1
0
At block-transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
Multi-Frame
1
At end of frame and end of block (DMCTRn = 0)
Either
0
X
No interrupt generated
Either
0
X
No interrupt generated
3.3.5.10.1DMA Controller Synchronization Events
The internal transfers associated with each DMA channel can be synchronized to one of several events. The
DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible
events and the DSYN values are shown in Table 313.
Table 313. DMA Synchronization Events
DSYN VALUE
DMA SYNCHRONIZATION EVENT
0000b
No synchronization used
0001b
McBSP0 receive event
0010b
McBSP0 transmit event
0011b
McBSP2 receive event
0100b
McBSP2 transmit event
0101b
McBSP1 receive event
0110b
McBSP1 transmit event
0111b
Reserved
1000b
Reserved
1001b
Reserved
1010b
Reserved
1011b
Reserved
1100b
Reserved
1101b
Timer interrupt event
1110b
External interrupt 3
1111b
Reserved
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