參數(shù)資料
型號： TMS570LS10216ASZWTQR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PBGA337
封裝： GERRN, PLASTIC, NFBGA-337
文件頁數(shù)： 46/102頁
文件大?。?/td> 1146K
代理商： TMS570LS10216ASZWTQR
PRODUCTPREVIEW
SPNS141D – AUGUST 2010 – REVISED JANUARY 2011
www.ti.com
4.6
MIBSPI
4.6.1
MIBSPI Event Trigger Sources
The Multi-buffered Serial Peripheral Interfaces (MIBSPIs) have a programmable buffer memory that
enables data transmission to be completed without CPU intervention. The buffers are combined in
different Transfer Groups (TGs) that can be triggered by external events such as I/O activity, timers or by
the internal tick counter. The internal tick counter supports the periodic trigger of events. Each buffer of the
MibSPI can be associated with different DMA channels in different TGs, allowing the user to move data
between internal memory and an external slave with minimal CPU interaction.
Table 4-8. MIBSPI1 Event Trigger Sources
Event
TGxCTRL TRIGSRC[3:0]
Hookup
Disabled
0000
No trigger source
EVENT0
0001
GIOA[0]
EVENT1
0010
GIOA[1]
EVENT2
0011
GIOA[2]
EVENT3
0100
GIOA[3]
EVENT4
0101
GIOA[4]
EVENT5
0110
GIOA[5]
EVENT6
0111
GIOA[6]
EVENT7
1000
GIOA[7]
EVENT8
1001
NHET[8]
EVENT9
1010
NHET[10]
EVENT10
1011
NHET[12]
EVENT11
1100
NHET[14]
EVENT12
1101
NHET[16]
EVENT13
1110
NHET[18]
EVENT14
1111
Internal Tick counter
Table 4-9. MIBSPI3 Event Trigger Sources
Event
TGxCTRL TRIGSRC[3:0]
Hookup
Disabled
0000
No trigger source
EVENT0
0001
GIOA[0]
EVENT1
0010
GIOA[1]
EVENT2
0011
GIOA[2]
EVENT3
0100
GIOA[3]
EVENT4
0101
GIOA[4]
EVENT5
0110
GIOA[5]
EVENT6
0111
GIOA[6]
EVENT7
1000
GIOA[7]
EVENT8
1001
NHET[8]
EVENT9
1010
NHET[10]
EVENT10
1011
NHET[12]
EVENT11
1100
NHET[14]
EVENT12
1101
NHET[16]
EVENT13
1110
NHET[18]
EVENT14
1111
Internal Tick counter
48
Peripherals
Copyright 2010–2011, Texas Instruments Incorporated
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