參數(shù)資料
型號： TMS570LS10216ASZWTQR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PBGA337
封裝： GERRN, PLASTIC, NFBGA-337
文件頁數(shù)： 84/102頁
文件大小： 1146K
代理商： TMS570LS10216ASZWTQR
PRODUCTPREVIEW
SPNS141D – AUGUST 2010 – REVISED JANUARY 2011
www.ti.com
7.10 SPI Slave Mode Timing Parameters
7.10.1 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input,
SPISIMO = input, and SPISOMI = output)
Table 7-15. SPI Slave Mode External Timing Parameters (1)(2)(3)
NO.
MIN
MAX
Unit
1
tc(SPC)S
Cycle time, SPICLK(4)
90
ns
2(5)
tw(SPCH)S
Pulse duration, SPICLK high(clock polarity = 0)
30
ns
tw(SPCL)S
Pulse duration, SPICLK low(clock polarity = 1)
30
3(5)
tw(SPCL)S
Pulse duration, SPICLK low(clock polarity = 0)
30
ns
tw(SPCH)S
Pulse duration, SPICLK high(clock polarity = 1)
30
4(5)
td(SPCH-SOMI)S
Delay time, SPISOMI valid after SPICLK high
trf(SOMI) + 15
ns
(clock polarity = 0)
td(SPCL-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
trf(SOMI) + 15
polarity = 1)
5(5)
tV(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
0
ns
(clock polarity =0)
tV(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
0
(clock polarity =1)
6(5)
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low(clock
4
ns
polarity = 0)
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high(clock
4
polarity = 1)
7(5)
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK low
6
ns
(clock polarity = 0)
th(SPCH-SIMO)S
Hold time, SPISIMO data valid after S PICLK high
6
(clock polarity = 1)
8
td(SPCL-SENAH)S
Delay time, SPIENAn high after last SPICLK low
1.5tc(VCLK)
2.5tc(VCLK)+tr(ENAn)+ 26
ns
(clock polarity = 0)
td(SPCH-SENAH)S
Delay time, SPIENAn high after last SPICLK high
1.5tc(VCLK)
2.5tc(VCLK)+tr(ENAn)+ 26
(clock polarity = 1)
9
td(SCSL-SENAL)S
Delay time, SPIENAn low after SPICSn low (if new
tf(ENAn)
tc(VCLK) + tf(ENAn)+ 18
ns
data has been written to the SPI buffer)
(1)
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2)
tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(3)
For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4)
When the SPI is in Slave mode, the following must be true:
tc(SPC)S > 2tc(VCLK) and tc(SPC)S>= 90 ns.
tw(SPCH)S > tc(VCLK) and tw(SPCL)S > tc(VCLK).
(5)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
82
Peripheral and Electrical Specifications
Copyright 2010–2011, Texas Instruments Incorporated
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