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SPNS141D – AUGUST 2010 – REVISED JANUARY 2011
Electrical Characteristics Over Operating Free-Air Temperature Range (continued)
Parameter
Test Conditions
MIN
TYP
MAX
Unit
ICC
(3)
VCC Digital
All packages
HCLK = 100MHz, VCLK = 100MHz
350
mA
supply current
HCLK = 140MHz, VCLK= 70MHz
390
mA
(Operating
BGA packages
HCLK = 160MHz, VCLK = 80MHz
430
mA
mode)
VCC Digital
All packages
STCCLK = 46.666MHz
Peak
510
mA
supply current
STCCLK = 50.0MHz
Peak
540
mA
(CPU selftest
BGA packages
STCCLK = 53.333MHz
Peak
580
mA
mode:
LBIST)(4)(5)
VCC Digital
All packages
HCLK=80MHz,
Peak
340
mA
supply current
VCLK=40MHz
(Mem selftest
HCLK=100MHz,
Peak
430
mA
mode:
VLCK=100MHz
PBIST)(4)(6)
VCC Digital supply current (doze mode)
OSCIN = 6 MHz, VCC = 1.65 V
(7)
35
mA
VCC Digital supply current (snooze mode)
All frequencies, VCC = 1.65 V
(7)
30
mA
VCC Digital supply current (sleep mode)
All frequencies, VCC = 1.65 V
(7)
25
mA
ICCIO
VCCIO Digital supply current (operating
No DC load, VCCIO = 3.6 V
(8)
15
mA
mode)
VCCIO Digital supply current (doze mode)
No DC load, VCCIO = 3.6 V
(8)
700
A
VCCIO Digital supply current (snooze
No DC load, VCCIO = 3.6 V
(8)
100
A
mode)
VCCIO Digital supply current (sleep mode)
No DC load, VCCIO = 3.6 V
(8)
100
A
ICCAD
VCCAD supply current (operating mode)
All frequencies, VCCAD = 3.6 V
30
mA
VCCAD supply current (doze mode)
All frequencies, VCCAD = 3.6 V
(7)
200
A
VCCAD supply current (snooze mode)
All frequencies, VCCAD = 3.6 V
(7)
200
A
VCCAD supply current (sleep mode)
All frequencies, VCCAD = 3.6 V
(7)
200
A
ICCP
VCCP pump supply current
VCCP = 3.6 V read operation
25
mA
VCCP = 3.6 V program
(9)
90
mA
VCCP = 3.6 V erase
90
mA
VCCP = 3.6 V doze mode
(10)
5
A
VCCP = 3.6 V snooze mode
(10)
5
A
VCCP = 3.6 V sleep mode
(10)
5
A
CI
Input
2
pF
capacitance(11)
CO
Output
3
pF
capacitance
(3)
Typical values are at Vcc=1.5V and maximum values are at Vcc=1.65V
(4)
The peak current is measured on the TI EVM board with two 10F and thirteen 100nF capacitors on VCC domain. Running at a lower
frequency consumes less current.
(5)
LBIST currents specified are for execution of LBIST with a certain STC clock. Lower current consumption can be achieved by
configuring a slower STC Clock frequency. The current peak duration can last for the duration of 1 LBIST test interval.
(6)
PBIST currents specified are for execution of PBIST on all RAMs(Group 1- 14) and all the algrithms. Lower current consumption can be
achieved by configuring a slower HCLK frequency. Different algorithms consume different current. For more information, please refer to
Basic PBIST Configuration and influence on current consumption (SPNA128).
(7)
For Flash banks/pumps in sleep mode.
(8)
I/O pins configured as inputs or outputs with no load. All pulldown inputs
≤ 0.2 V. All pullup inputs ≥ VCCIO - 0.2 V.
(9)
This assumes reading from one bank while programming a different bank.
(10) For Flash banks/pumps in sleep mode.
(11) The maximum input capacitance CI of the FlexRay RX pin(s) is 10pF.
Copyright 2010–2011, Texas Instruments Incorporated
Device Electrical Specifications
65