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參數(shù)資料
| 型號(hào)： | TMS570LS10216ASZWTQR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PBGA337 |
| 封裝： | GERRN, PLASTIC, NFBGA-337 |
| 文件頁(yè)數(shù)： | 73/102頁(yè) |
| 文件大小： | 1146K |
| 代理商： | TMS570LS10216ASZWTQR |
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PRODUCTPREVIEW
SPNS141D – AUGUST 2010 – REVISED JANUARY 2011
www.ti.com
7.3.2
Switching Characteristics Over Recommended Operating Conditions For RST
Table 7-7. Switching Characteristics Over Recommended Operating Conditions For RST(1)
Parameter
MIN
MAX
Unit
tv(RST)
Valid time, RST active after PORRST inactive
1048c(OSC)
ns
Valid time, RST active (all others)
8tc(VCLK)
(1)
Specified values do NOT include rise/fall times. For rise and fall timings, see the switching characteristics for output timings versus load
capacitance table.
7.3.3
IO Status During PORRST
IO buffer condition during power-on-reset (nPORRST is low): All I/O pins, except nRST, are configured as
High-impedance while nPORRST is low and immediately after nPORRST goes high. The FlexRay
FRAYTX1 and FRAYTX2 pins are high impedance (high-Z) while nPORRST is low, and are output high at
latest 1024 oscillator cycles after nPORRST goes high; the FlexRay FRAYTXEN1 and FRAYTXEN2 pins
are high impedance (high-Z) while nPORRST is low, and output high immediately after nPORRST goes
high.
IO pullup/pulldown condition during power-on-reset: all internal pullups and pulldowns on input pins are
disabled when nPORRST is low, and become active immediately after nPORRST goes high. Pins that are
listed with "programmable" have programmable pullups or pulldowns. The default value after reset is listed
underneath "programmable" in the following table. The exceptions are nPORRST, nRST, nTRST and
TEST pins. The pulls on these pins will be active during power-on-reset.
72
Peripheral and Electrical Specifications
Copyright 2010–2011, Texas Instruments Incorporated
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