參數(shù)資料
型號(hào): TMS570LS10216ASZWTQR
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PBGA337
封裝: GERRN, PLASTIC, NFBGA-337
文件頁(yè)數(shù): 95/102頁(yè)
文件大小: 1146K
代理商: TMS570LS10216ASZWTQR
PRODUCTPREVIEW
t(RTP)disable
t(RTP)enable
HCLK
RTPCLK
RTPENA
RTPSYNC
RTPDATA
t(RTP)disable
t(RTP)enable
HCLK
RTPCLK
RTPENA
RTPSYNC
RTPDATA
t(RTP)enable
t(RTP)disable
HCLK
RTPCLK
RTPENA
RTPSYNC
RTPDATA
d1
d2
d3
d4
d5
d6
d7
d8
Divide by 1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SPNS141D – AUGUST 2010 – REVISED JANUARY 2011
www.ti.com
7.16.3 RTPENABLE Timing
Figure 7-23. RTPENABLE Timing
Table 7-24. RTPENABLE Timing
Parameter
Minimum
Maximum
Description
t(RTP)disable
1.5tc(HCLK) + tr(RTPSYNC) + 12ns
Time that RTPENA must go high
before the next scheduled
RTPSYNC in order to suspend
transmission for the packet
following the scheduled
RTPSYNC.
t(RTP)enable
4.5tc(HCLK) + tr(RTPSYNC)
5.5tc(HCLK) + tr(RTPSYNC) + 12ns
Time after RTPENA goes low
before a packet that has been
halted, resumes.
92
Peripheral and Electrical Specifications
Copyright 2010–2011, Texas Instruments Incorporated
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