參數(shù)資料
型號： TMS570LS10216ASZWTQR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PBGA337
封裝： GERRN, PLASTIC, NFBGA-337
文件頁數(shù)： 72/102頁
文件大?。?/td> 1146K
代理商： TMS570LS10216ASZWTQR
PRODUCTPREVIEW
3.3 V
1.5 V
CCIOPORL
PORRST
VCC (1.5 V)
6
VCCPORH
V
VIL(PORRST)
VCCIOPORH
VCCIOPORL
VCCPORL
VCC
VCCIO / VCCP
VCCPORH
VCCPORL
VIL
VIL(PORRST)
8
7
6
3
7
9
www.ti.com
SPNS141D – AUGUST 2010 – REVISED JANUARY 2011
7.3
RST And PORRST Timings
7.3.1
Timing Requirements For PORRST
Table 7-6. Timing Requirements For PORRST
NO.
MIN
MAX
Unit
VCCPORL
VCC low supply level when PORRST must be active during power up
0.5
V
VCCPORH
VCC high supply level when PORRST must remain active during power up
1.35
V
and become active during power down
VCCIOPORL
VCCIO / VCCP low supply level when PORRST must be active during
1.1
V
power up
VCCIOPORH
VCCIO / VCCP high supply level when PORRST must remain active during
3
V
power up and become active during power down
VIL(PORRST)
Low-level input voltage of PORRST VCCIO > 2.5V
0.2 VCCIO
V
Low-level input voltage of PORRST VCCIO< 2.5V
0.5
V
3
tsu(PORRST)
Setup time, PORRST active before VCCIO and VCCP > VCCIOPORL during
0
ms
power up
6
th(PORRST)
Hold time, PORRST active after VCC > VCCPORH
1
ms
7
tsu(PORRST)
Setup time, PORRST active before VCC <= VCCPORH during power down
8
s
8
th(PORRST)
Hold time, PORRST active after VCCIO and VCCP > VCCIOPORH
1
ms
9
th(PORRST)
Hold time, PORRST active after VCC < VCCPORL
0
ms
tf(PORRST)
Filter time PORRST, pulses less than MIN will be filtered out, pulses
20
150
ns
greater than MAX are guaranteed to generate a reset(1)
tf(RST)
Filter time RST, pulses less than MIN will be filtered out, pulses greater
20
150
ns
than MAX are guaranteed to generate a reset
(1)
The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,
I/O pins, etc.) without also generating a valid reset signal to the CPU.
Figure 7-5. PORRST Timing Diagram
NOTE
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage;
this is just an exemplary drawing. All requirements are to ensure PORRST is active when
VCCIO or VCC is out of the normal operating range.
Copyright 2010–2011, Texas Instruments Incorporated
Peripheral and Electrical Specifications
71
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