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P
6.19.2
Timer Electrical Data/Timing
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-94. Timer 2 (Watchdog) Registers
HEX ADDRESS RANGE
0x01C2 1C00
0x01C2 1C04
0x01C2 1C10
0x01C2 1C14
0x01C2 1C18
0x01C2 1C1C
0x01C2 1C20
0x01C2 1C24
0x01C2 1C28
0x01C2 1C2C - 0x01C2 1FFF
ACRONYM
-
EMUMGT_CLKSPD
TIM12
TIM34
PRD12
PRD34
TCR
TGCR
WDTCR
-
DESCRIPTION
Reserved
Timer 2 Emulation Management/Clock Speed Register
Timer 2 Counter Register 12
Timer 2 Counter Register 34
Timer 2 Period Register 12
Timer 2 Period Register 34
Timer 2 Control Register
Timer 2 Global Control Register
Timer 2 Watchdog Timer Control Register
Reserved
Table 6-95. Timing Requirements for Timer Input
(1)(2)(3)
(see
Figure 6-52
)
-400
-500
-600
MIN
NO.
UNIT
MAX
TINP0L, if TIMERCTL.TINP0SEL = 0
[default]
TINP0L, if TIMERCTL.TINP0SEL = 1
TINP1L
TINP0L, if TIMERCTL.TINP0SEL = 0
[default]
TINP0L, if TIMERCTL.TINP0SEL = 1
TINP1L
2P
ns
1
t
w(TINPH)
Pulse duration, TINPxL high
0.33P
ns
ns
2P
2P
ns
2
t
w(TINPL)
Pulse duration, TINPxL low
0.33P
ns
ns
2P
(1)
(2)
P = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use P = 37.037 ns.
The TIMERCTL.TINP0SEL field in the System Module determines if the TINP0L input directly goes to Timer 0
(TIMERCTL.TINP0SEL=0), or if the TINP0L input is first divided down by 6 before going to Timer 0 (TIMERCTL.TINP0SEL=1).
TINP1L input goes directly to Timer 1.
(3)
Table 6-96. Switching Characteristics Over Recommended Operating Conditions for Timer Output
(1)
(see
Figure 6-52
)
-400
-500
-600
NO.
UNIT
MIN
MAX
3
4
t
w(TOUTH)
t
w(TOUTL)
P = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use P = 37.037 ns.
Pulse duration, TOUTxL high
Pulse duration, TOUTxL low
P
P
ns
ns
(1)
Peripheral Information and Electrical Specifications
284
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