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6.7.2
DSP Interrupts
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in
Table 6-22
. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts.
Table 6-23
summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP
interrupt control, see the
Documentation Support
section of the
TMS320DM6443 DMSoC DSP Subsystem
Reference Guide
(literature number
SPRUE15
).
Table 6-22. DM6443 DSP Interrupts
DSP
DSP
INTERRUPT
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
ACRONYM
SOURCE
INTERRUPT
NUMBER
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
ACRONYM
SOURCE
EVT0
EVT1
EVT2
EVT3
TINT0
TINT1
TINT2
TINT3
C64x+ Int Ctl 0
C64x+ Int Ctl 1
C64x+ Int Ctl 2
C64x+ Int Ctl 3
Timer 0 – TINT12
Timer 0 – TINT34
Timer 1 – TINT12
Timer 1 – TINT34
Reserved
C64x+ EMC
Reserved
C64x+ RTDX
C64x+ RTDX
C64x+ EMC 0
C64x+ EMC 1
Reserved
ARM to DSP Controller 0
ARM to DSP Controller 1
ARM to DSP Controller 2
ARM to DSP Controller 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
C64x+ Interrupt Controller
Dropped CPU Interrupt Event
C64x+ EMC Invalid IDMA
Parameters
Reserved
Reserved
EMU_DTDMA
EMU_RTDXRX
EMU_RTDXTX
IDMAINT0
IDMAINT1
ARM2DSP0
ARM2DSP1
ARM2DSP2
ARM2DSP3
INTERR
32
96
Reserved
EMC_IDMAERR
33
97
34
35
Reserved
Reserved
98
99
Peripheral and Electrical Specifications
114
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