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6.15 USB 2.0
6.15.1 USBPHY_CTL Register Description
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
The DM6443 USB2.0 peripheral supports the following features:
USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous)
4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
FIFO RAM
–
4K endpoint
–
Programmable size
Connects to a standard UTMI+ PHY with a 60 MHz, 8-bit interface
Connects to a standard Charge Pump for VBUS 5 V generation
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
The USB physical interface control register USBPHY_CTL is described in
Figure 6-55
and
Table 6-63
.
Figure 6-55. USBPHY_CTL Register
31
9
8
7
6
5
4
3
2
1
0
Reserved
PHYCLKGD
SESNDEN
VBDTCTEN
RSV
PHYPLLON
CLKO1SEL
OSCPDWN
RSV
PHYPDWN
R-0000 0000 0000 0000 0000 000
R-0
R/W-1
R/W-1
R-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
LEGEND: R = Read, W = Write, n = value at reset
Table 6-63. USBPHY_CTL Register Descriptions
Name
PHYCLKGD
Description
USB PHY Power and Clock Good
0 = Phy power not ramped or PLL not locked
1 = Phy power is good and PLL is locked
Session End Comparator enable
0 = comparator disabled
1 = comparator enabled
vbus comparator enable
0 = comparators (except session end) disabled
1 = comparators (except session end) enabled
USB PHY PLL suspend override
0 = Normal PLL operation
1 = Override PLL suspend state
CLK_OUT1 frequency select
0 = 24 MHz
1 = 12 MHz
USB PHY oscillator power down control
0 = PHY oscillator powered
1 = PHY oscillator power off
USB PHY power down control
0 = PHY powered
1 = PHY power off
SESNDEN
VBDTCTEN
PHYPLLON
CLKO1SEL
OSCPDWN
PHYPDWN
Peripheral and Electrical Specifications
176
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