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參數(shù)資料
| 型號： | TMX320DM6443ZWT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media System-on-Chip |
| 中文描述： | 數(shù)字媒體系統(tǒng)片上 |
| 文件頁數(shù)： | 12/221頁 |
| 文件大?。?/td> | 1582K |
| 代理商： | TMX320DM6443ZWT |
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2.3.5
Tightly Coupled Memory (TCM)
2.3.6
Advanced High-Performance Bus (AHB)
2.3.7
Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables.
Critical-word first cache refilling
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt
Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM
and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides
for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the
D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be
stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM
sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to
the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to
the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.
Instruction and Data accesses are differentiated via accessing different memory map regions, with the
instruction region from 0x0000 through 0x7FFF and data from 0x8000 through 0xFFFF. The instruction
region at 0x0000 and data region at 0x8000 map to the same physical 16KB TCM RAM. Placing the
instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,
as required by the ARM architecture. The internal 16-KB RAM is split into two physical banks of 8KB
each, which allows simultaneous instruction and data accesses to be accomplished if the code and data
are in separate banks.
The ARM926EJ-S has built in DMA support for direct accesses to the ARM internal memory from a non-
ARM device. Furthermore, because of the time critical nature of the TCM link to the ARM internal memory,
all accesses from non-ARM devices are treated as DMA transfers.
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the DM6443 also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
Trace Port provides real-time trace capability for the ARM9.
Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
Device Overview
12
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320DM6444AZWT | 制造商:Texas Instruments 功能描述:TMS320DM6443, TMS320DM6444 DIGITAL MEDIA SOC DATA SHEET - Trays |
| TMX320DM6446AZWT | 制造商:Texas Instruments 功能描述: |
| TMX320DM6446AZWT8 | 制造商:Texas Instruments 功能描述:DAVINCI REL 2.1 810 MHZ - Trays |
| TMX320DM6446AZWTA | 制造商:Texas Instruments 功能描述:DAVINCI DIGITAL MEDIA SYSTEM-ON-CHIP - Trays |
| TMX320DM6446BZWT | 制造商:Texas Instruments 功能描述:SYS-ON-CHIP PROCESSOR 361PIN NFBGA - Trays |
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