
www.ti.com
3.6 Emulation Control
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
The flexibility of the DM644x architecture allows either the ARM or DSP to control the various peripherals
(setup registers, service interrupts, etc.). While this assignment is purely a matter of software convention,
during an emulation halt it is necessary for the device to know which peripherals are associated with the
halting processor so that only those modules receive the suspend signal. This allows peripherals
associated with the other (unhalted) processor to continue normal operation. The SUSPSRC register
indicates the emulation suspend source for those peripherals which support emulation suspend. The
SUSPSRC register format is shown in
Figure 3-9
. Brief details on the peripherals which correspond to the
register bits is given in
Table 3-33
. When the associated SUSPSRC bit is ‘0’, the peripheral’s emulation
suspend signal is controlled by the ARM emulator and when set to ‘1’ it is controlled by the DSP emulator.
Figure 3-9. Emulation Suspend Source Register (SUSPSRC)
(1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TIMR2
SRC
TIMR1
SRC
TIMR0
SRC
GPIO
SRC
PWM2
SRC
PWM1
SRC
PWM0
SRC
SPI
SRC
UART2
SRC
UART1
SRC
UART0
SRC
I2C
SRC
ASP
SRC
Rsvd
Rsvd
Rsvd
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
15
13
12
11
10
9
8
6
5
4
0
HPI
SRC
USB
SRC
EMAC
SRC
Reserved
Reserved
Reserved
Reserved
R-000
R/W-0
R-00
R/W-0
R-000
R/W-0
R-0 0000
LEGEND: R = Read, W = Write, n = value at reset
(1)
For proper DM6443 device operation,
always
write a value of '0' to RSV bits 30 and 31.
Table 3-33. SUSPSRC Register Description
Name
TIMR2SRC
Description
Timer2 (WD Timer) emulation suspend source
0 = ARM emulation suspend
Timer1 emulation suspend source
0 = ARM emulation suspend
Timer0 emulation suspend source
0 = ARM emulation suspend
GPIO emulation suspend source
0 = ARM emulation suspend
PWM2 emulation suspend source
0 = ARM emulation suspend
PWM1 emulation suspend source
0 = ARM emulation suspend
PWM0 emulation suspend source
0 = ARM emulation suspend
SPI emulation suspend source
0 = ARM emulation suspend
UART2 emulation suspend source
0 = ARM emulation suspend
UART1 emulation suspend source
0 = ARM emulation suspend
UART0 emulation suspend source
0 = ARM emulation suspend
I2C emulation suspend source
0 = ARM emulation suspend
ASP emulation suspend source
0 = ARM emulation suspend
1 = DSP emulation suspend
TIMR1SRC
1 = DSP emulation suspend
TIMR0SRC
1 = DSP emulation suspend
GPIOSRC
1 = DSP emulation suspend
PWM2SRC
1 = DSP emulation suspend
PWM1SRC
1 = DSP emulation suspend
PWM0SRC
1 = DSP emulation suspend
SPISRC
1 = DSP emulation suspend
UART2SRC
1 = DSP emulation suspend
UART1SRC
1 = DSP emulation suspend
UART0SRC
1 = DSP emulation suspend
I2CSRC
1 = DSP emulation suspend
ASPSRC
1 = DSP emulation suspend
Device Configurations
80
Submit Documentation Feedback