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Revision History
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
This data manual revision history highlights the technical changes made to the SPRS282D device-specific
data manual to make it an SPRS282E revision.
Scope:
Applicable updates to the DM64x device family, specifically relating to the TMS320DM6443
device, have been incorporated.
TMS320DM6443 Revision History
SEE
Global
Section 1.1
ADDITIONS/MODIFICATIONS/DELETIONS
Changed instances of MMC/SD to MMC/SD
/SDIO
to indicate secure data I/O support
Features:
Added
Secure Data I/O (SDIO)
under Flash Card Interfaces
Added
Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data
Description:
Updated paragraph, The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 . . .
Functional Block Diagram:
Added HPI and SDIO to
Figure 1-1
, TMS320DM6443 Functional Block Diagram
Characteristics of the Processor:
Updated description for Peripherals Flash Cards
Added row for HPI Peripheral
Added row for C64x+ Megamodule Revision feature
Memory Map Summary:
Added HPI column to
Table 2-3
, Memory Map Summary
Deleted AET Registers from address 0x01BC 0000 and replaced with Reserved in
Table 2-4
,
Configuration Memory Map Summary
Added HPI to address 0x01C6 7800 in
Table 2-4
, Configuration Memory Map Summary
Pin Map (Bottom View):
Updated
Figure 2-5
, Pin Map [Quadrant D]
Terminal Functions:
Added HPI Signal Names and Descriptions for multiplexed pins in
Table 2-9
, EMIFA Terminal Functions
Updated Descriptions in
Table 2-6
, Oscillator/PLL Terminal Functions
Updated Descriptions in
Table 2-17
, USB Terminal Functions
Updated Descriptions in
Table 2-20
, DAC [Part of VPBE] Terminal Functions
Changed title of
Table 2-24
to MMC/SD
/SDIO
Terminal Functions
Added
Table 2-25
, HPI Terminal Functions
System Module Registers:
Changed address 0x01C4 0028 to JTAGID register
Added HPI_CTL register and description to address 0x01C4 0030 in
Table 3-1
, System Module Register
Memory Map
BOOTCFG Register Description:
Changed bit field BTSEL description for value 10 in
Table 3-4
, BOOTCFG Register Description
ARM Boot:
Updated paragraphs
Updated
Table 3-6
, ARM Boot Modes
DSP Boot:
Added row for HPI to
Table 3-7
, DSP Boot Modes
Device Configuration at Device Reset:
Changed description for value 10 in
Table 3-8
, Device Configurations (Input Pins Sampled at Reset)
Switched Central Resource (SCR) Bus Priorities:
Added row for HPI in
Table 3-12
, DM6443 Default Bus Master Priorities
Multiplexed Pin Configurations:
Added HPI pin information to
Table 3-13
, DM6443 Multiplexed Peripheral Pins and Multiplexing Controls
PINMUX0 Register Description:
Added HPIEN to bit field 29 in
Figure 3-7
, PINMUX0 Register
Added HPIEN description to
Table 3-14
, PINMUX0 Register Description
Pin Multiplexing Register Field Details
Added new
Section 3.5.6.10
,
HPI and EMIFA/ATA Pin Multiplexing
Emulation Control:
Added HPISRC to bit field 12 in
Figure 3-9
, Emulation Suspend Source Register (SUSPSRC)
Added bit field HPISRC description to
Table 3-33
, SUSPSRC Register Description
Section 1.2
Section 1.3
Table 2-1
Section 2.5
Section 2.6.1
Section 2.7
Section 3.1
Section 3.3.1.1
Section 3.3.2
Section 3.3.3
Section 3.4.1
Section 3.5.1
Section 3.5.2
Section 3.5.4
Section 3.5.6
Section 3.6
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Revision History
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