參數(shù)資料
型號(hào)： TTRN0110G
英文描述： ATM MULTIPLEXER|BGA|198PIN|CERAMIC
中文描述： ATM多路復(fù)用器|的BGA | 198PIN |陶瓷
文件頁(yè)數(shù)： 14/30頁(yè)
文件大?。?/td> 578K
代理商： TTRN0110G
14
Agere Systems Inc.
Data Sheet
March 29, 2002
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0110G
Multiplexer Operation
The parallel 622 Mbits/s data is clocked into an input buffer, then clocked into a 16:1 multiplexer. The relationship
between the parallel D[15:0]P/N input data and the serial output data D10GP/N is given in Figure 5. The D15 bit is
the most significant bit (MSB) and is shifted out first in time in the serial output stream.
5-8063(F)
Figure 5. Parallel Input to Serial Output Data Relationship
10 GHz Clock Output Enable (ENCK10G)
The 10 GHz CML clock output CK10GP/N may be disabled by setting the ENCK10G pin to logic low. ENCK10G is
an active-high CMOS input with an internal pull-up resistor so the default condition will enable the CK10GP/N
output and a ground or logic-low signal must be applied to disable the CK10GP/N output. When disabled, the
CK10GP/N pins should either be left floating or be connected to a load, which returns to V
CC
. The output must not
be connected directly to ground when it is disabled.
Loopback 10 GHz Data Output (LBDP/N, ENLBDN)
An alternate 10 Gbits/s CML data output is available on the LBDP/N pin. This pin is provided for use in system
loopback testing and avoids the need for off-chip signal splitting of the data signal path. Setting the ENLBDN pin to
logic-low will enable the alternate 10 Gbits/s loopback data output. ENLBDN enable is an active-low CMOS input
with an internal pull-up resistor so the default condition will disable the LBDP/N output, and a ground or logic-low
signal must be applied to enable the loopback output. When disabled, the LBDP/N pin should either be left floating,
or be connected to a load which returns to V
CC
. The output must not be connected directly to ground when it is
disabled.
Reset (RESETN)
The RESETN signal must be held active-low for a minimum of 6.4 ns when the internal VCO is active and running,
in order for the internal logic to be completely reset.
D15
(MSB)
D14
D1
D0
D15
TIME
(D15 SERIALLY SHIFTED OUT FIRST)
(D0 SERIALLY SHIFTED OUT LAST)
(LSB)
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