參數(shù)資料
型號(hào)： TTRN0110G
英文描述： ATM MULTIPLEXER|BGA|198PIN|CERAMIC
中文描述： ATM多路復(fù)用器|的BGA | 198PIN |陶瓷
文件頁(yè)數(shù)： 17/30頁(yè)
文件大?。?/td> 578K
代理商： TTRN0110G
Agere Systems Inc.
17
Data Sheet
March 29, 2002
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0110G
Clocking Modes and Timing Adjustments
(continued)
Clockless Transfer Mode (CLKMOD[1:0]= 11, EXTCNTR)
In clockless transfer mode (CLKMOD[1:0] = 11), data may be sent to the TTRN0110G device without providing
PICLKP/N. An internal delay-locked loop (DLL) automatically produces a 622 MHz clock that is aligned to the
parallel data based on the phase of the D0P/N data input. The skew of all data bits D[15:1]P/N relative to D0P/N
must be less than 650 ps, as shown in Figure 11 on page 24.
An internal data buffer is used to absorb timing drift between D0 and the internal clocks derived from the 10 GHz
internal oscillator. A D0 phase drift of up to ±1600 ps relative to the internal clocks can be absorbed by the buffer,
as long as the bandwidth of this phase drift is less than 500 kHz.
Note:
The read and write addresses for the data buffer must be initially reset in order for the buffer to absorb the
full range of D[15:0]P/N phase drift.
The read and write addresses for the data buffer are reset at the time the PLL acquires lock and the loss-of-lock
indicator transitions from the out-of-lock condition to the in-lock condition. After LCKLOSSN goes high, the buffer
will be centered and data integrity will be obtained within approximately 2
μ
s.
The data buffer can also be recentered by applying EXTCNTR (active-high) for a minimum of 6.4 ns. After
EXTCNTR goes low, the buffer will be centered and data integrity will be lost and subsequently restored within
approximately 2
μ
s.
If the timing drift exceeds ±1600 ps, the data buffer will indicate overflow with a logic-high signal on the OVRFLW
pin for a minimum of 6.4 ns. After a time interval of 4.8 ns after OVRFLW goes low, the buffer will be recentered
and data integrity will be lost and subsequently restored within approximately 2
μ
s. During the 11.2 ns between the
rising edge of OVRFLW and the recentering of the buffer, data integrity may be lost if the timing drift exceeds
±2000 ps.
If the output clock CK622P/N is not used when in CLKMOD[1:0] = 11, it can be left unconnected to conserve
power.
Because the clockless data transfer mode uses the transitions on the D0 data bit as a phase reference for clocking
the data, a constraint of a maximum number of consecutive zeros of less than 128 data periods is placed on the D0
bit when operating in the clockless data transfer mode.
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