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參數(shù)資料
| 型號： | TTRN0110G |
| 英文描述： | ATM MULTIPLEXER|BGA|198PIN|CERAMIC |
| 中文描述： | ATM多路復用器|的BGA | 198PIN |陶瓷 |
| 文件頁數(shù)： | 26/30頁 |
| 文件大?。?/td> | 578K |
| 代理商： | TTRN0110G |
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26
Agere Systems Inc.
Data Sheet
March 29, 2002
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0110G
Timing Characteristics
(continued)
Transmit Timing
(continued)
Figure 12 shows the timing relationships between the output 10 GHz clock CK10GP/N and the output 10 Gbits/s
data D10GP/N.
0357(F)
Figure 12. Transmit Timing Waveform with 10 GHz Clock
The output 10 GHz clock and data signals from Figure 12 are characterized in Table 21.
Table 21. CML Output Pin ac Timing Characteristics
Applicable
Pins
CK10GP/N
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
Duty Cycle
CK10GP/N Clock Period
Time Delay from Clock
Edge to Data Edge
Rise Time, 20% to 80%
Fall Time, 20% to 80%
Differential Skew
Output Return Loss:
10 GHz
<7 GHz
Voltage Amplitude Single-
ended
RREFCML = 3 k
,
R
L
= 50
40
—
30
50
100
50
60
—
70
%
ps
ps
t
PERIOD
t
DD
D10GP/N,
CK10GP/N
CK10GP/N
D10GP/N,
LBDP/N
t
RISE
t
FALL
t
SKEW1
R
LOSS
10
10
—
20
—
35
35
3
ps
ps
ps
—
—
—
—
600
12
15
—
—
—
800
dB
dB
mV
D10GP/N,
LBDP/N
V
AMP
RREFCML = 2.2 k
,
R
L
= 50
RREFCML = 3.0 k
,
R
L
= 50
RREFCML = 3.5 k
,
R
L
= 50
RREFCML = 2.2 k
,
R
L
= 50
RREFCML = 3 k
,
R
L
= 50
RREFCML = 3.5 k
,
R
L
= 50
450
—
650
mV
350
—
500
mV
CK10GP/N
V
AMP
Voltage Amplitude Single-
ended
800
—
1.0 V
mV
600
—
800
mV
500
—
650
mV
CK10GP/N
D10GP/N
OUTPUT
OUTPUT
DATA 1
DATA 2
tPERIOD
tDD
DATA 3
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