- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366034 > TTRN0110G ATM MULTIPLEXER|BGA|198PIN|CERAMIC PDF資料下載
參數(shù)資料
| 型號(hào)： | TTRN0110G |
| 英文描述： | ATM MULTIPLEXER|BGA|198PIN|CERAMIC |
| 中文描述： | ATM多路復(fù)用器|的BGA | 198PIN |陶瓷 |
| 文件頁數(shù)： | 16/30頁 |
| 文件大小： | 578K |
| 代理商： | TTRN0110G |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
16
Agere Systems Inc.
Data Sheet
March 29, 2002
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0110G
Clocking Modes and Timing Adjustments
(continued)
Contradirectional Clocking Mode (CLKMOD[1:0] = 01, PHADJ[1:0], EXTCNTR)
In the contradirectional clocking mode (CLKMOD[1:0] = 01), the TTRN0110G device sends a 622 MHz clock with
one of four user-selectable phases out to the upstream device for clocking the data toward the TTRN0110G. The
user can program PHADJ[1:0] to adjust the phase of CK622P/N as a function of printed wiring board (PWB) layout
and upstream device propagation delay in order to meet the setup and hold time of the 622 Mbits/s data input to
the TTRN0110G. PHADJ[1:0] changes the phase of the CK622P/N clock without changing the input data sampling
time. PHADJ[1:0] setting information is given in Table 8, and the phase relationship of CK622P/N for each
PHADJ[1:0] setting is shown in Figure 6.
Table 8. PHADJ Settings for CK622 Output Clock (Contraclocking Mode)
In this mode, the TTRN0110G input data still passes through the data buffer described in the forward directional
clocking sections; however, there will no longer be any phase drift or overflow since the CK622P/N output serves
as the master clock for the upstream device. The read and write addresses for the data buffer are initially reset
at the time the PLL acquires lock and the loss-of-lock indicator transitions from the out-of-lock condition to the in-
lock condition. After LCKLOSSN goes high, the buffer will be recentered and data integrity will be obtained within
approximately 2
μ
s.
5-8064(F)
Figure 6. CK622 Phase Relation vs. PHADJ Setting
Input Pins
Phase
PHADJ[1]
0
0
1
1
PHADJ[0]
0
1
0
1
0 (See part A of Figure 6.)
–270 (See part D of Figure 6.)
–180 (See part C of Figure 6.)
–90 (See part B of Figure 6.)
A. (0 DEG.)
B. (–90 DEG.)
C. (–180 DEG.)
D. (–270 DEG.)
TIME
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TTSAL | Crystal Oscillator |
| TU0425W-20 | TUBING 4MM WHITE 20M |
| TCU0425B-1 | Transient Voltage Suppressor Diodes |
| TCU0425B-2 | Transient Voltage Suppressor Diodes |
| TCU0425B-3 | Transient Voltage Suppressor Diodes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TTRN012G5 | 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer |
| TTRN012G53XE1 | 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer |
| TTRN012G7 | 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer |
| TTRN012G73XE1 | 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer |
| TTR-RED | 功能描述:打印機(jī) Ribbon, Resin, 4.33" W x 299’ L, for use RoHS:否 制造商:Seiko Instruments 產(chǎn)品:Printer 電源電壓: 每行點(diǎn)數(shù):9 x 320 打印速度:52.5 cps, 80 cps 紙張寬度:112 mm |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。