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參數(shù)資料
| 型號： | TTRN0110G |
| 英文描述： | ATM MULTIPLEXER|BGA|198PIN|CERAMIC |
| 中文描述： | ATM多路復(fù)用器|的BGA | 198PIN |陶瓷 |
| 文件頁數(shù)： | 15/30頁 |
| 文件大小： | 578K |
| 代理商： | TTRN0110G |
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Agere Systems Inc.
15
Data Sheet
March 29, 2002
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0110G
Clocking Modes and Timing
Adjustments
The TTRN0110G supports four timing modes for the
622 Mbits/s data input: forward directional 622, forward
directional 311, contradirectional, and clockless
transfer, as selected by the CLKMOD[1:0] pins.
Forward Directional 622 Clocking Mode
(CLKMOD[1:0] = 00, EXTCNTR, PICLKP/N,
OVRFLW)
In forward directional 622 clocking mode
(CLKMOD[1:0] = 00), data is clocked into a 16-bit wide
input register on the TTRN0110G device by the
PICLKP/N parallel input clock. The setup and hold
times for the data relative to PICLK are given in
Figure 8 on page 23 and Table 19 on page 25. An
internal data buffer is used to absorb timing drift
between PICLK and the internal clocks derived from
the 10 GHz internal oscillator. A PICLK phase drift of
up to ±2400 ps relative to the internal clocks can be
absorbed by the buffer, as long as the bandwidth of this
phase drift is less than 500 kHz. Note that the read and
write addresses for the data buffer must be initially
reset in order for the buffer to absorb the full range of
PICLK phase drift.
The read and write addresses for the data buffer are
reset at the time the PLL acquires lock and the loss-of-
lock indicator transitions from the out-of-lock condition
to the in-lock condition. After LCKLOSSN goes high,
the buffer will be centered and data integrity will be
obtained within approximately 2
μ
s.
The data buffer can also be recentered by applying
EXTCNTR (active-high) for a minimum of 6.4 ns. After
EXTCNTR goes low, the buffer will be centered and
data integrity will be lost and subsequently restored
within approximately 2
μ
s.
If the timing drift exceeds ±2400 ps, the data buffer will
indicate overflow with a logic-high signal on the
OVRFLW pin for a minimum of 6.4 ns. After a time
interval of 4.8 ns after OVRFLW goes low, the buffer
will be recentered and data integrity will be lost and
subsequently restored within approximately 2
μ
s.
During the 11.2 ns between the rising edge of
OVRFLW and the recentering of the buffer, data
integrity may be lost if the timing drift exceeds
±2000 ps.
If the output clock CK622P/N is not used when in
CLKMOD[1:0] = 00, it can be left unconnected to
conserve power.
Forward Directional 311 Clocking Mode
(CLKMOD[1:0] = 10, EXTCNTR, PICLKP/N,
OVRFLW)
In forward directional 311 clocking mode
(CLKMOD[1:0] = 10), data is clocked into a 16-bit wide
input register on the TTRN0110G device by the
PICLKP/N parallel input clock. In contrast to forward
directional 622 mode, the PICLK signal is at half the
data rate (311 MHz instead of 622 MHz). The setup
and hold times for the data relative to PICLK are given
in Figure 9 on page 23 and Table 19 on page 25. An
internal data buffer is used to absorb timing drift
between PICLK and the internal clocks derived from
the 10 GHz internal oscillator. A PICLK phase drift of
up to ±2400 ps relative to the internal clocks can be
absorbed by the buffer, as long as the bandwidth of this
phase drift is less than 500 kHz. Note that the read and
write addresses for the data buffer must be initially
reset in order for the buffer to absorb the full range of
PICLK phase drift.
The read and write addresses for the data buffer are
reset at the time the PLL acquires lock and the loss-of-
lock indicator transitions from the out-of-lock condition
to the in-lock condition. After LCKLOSSN goes high,
the buffer will be centered and data integrity will be
obtained within approximately 2
μ
s.
The data buffer can also be recentered by applying
EXTCNTR (active-high) for a minimum of 6.4 ns. After
EXTCNTR goes low, the buffer will be centered and
data integrity will be lost and subsequently restored
within approximately 2
μ
s.
If the timing drift exceeds ±2400 ps, the data buffer will
indicate overflow with a logic-high signal on the
OVRFLW pin for a minimum of 6.4 ns. After a time
interval of 4.8 ns after OVRFLW goes low, the buffer
will be recentered and data integrity will be lost and
subsequently restored within approximately 2
μ
s.
During the 11.2 ns between the rising edge of
OVRFLW and the recentering of the buffer, data
integrity may be lost if the timing drift exceeds
±2000 ps.
If the output clock CK622P/N is not used when in
CLKMOD[1:0] = 10, it can be left unconnected to
conserve power.
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