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參數(shù)資料
| 型號： | TTRN0110G |
| 英文描述： | ATM MULTIPLEXER|BGA|198PIN|CERAMIC |
| 中文描述： | ATM多路復用器|的BGA | 198PIN |陶瓷 |
| 文件頁數(shù)： | 8/30頁 |
| 文件大?。?/td> | 578K |
| 代理商： | TTRN0110G |
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8
Agere Systems Inc.
Data Sheet
March 29, 2002
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0110G
Ball Information
(continued)
Ball Description
(continued)
Note:
In Table 3, when operating the TTRN0110G device at the OC-192/STM-64 rate, 622 Mbits/s and
155 Mbits/s should be interpreted as 622.08 Mbits/s and 155.52 Mbits/s, respectively. When operating the
TTRN0110G device at the Ethernet rate, 622 Mbits/s and 155 Mbits/s should be interpreted as
641.52 Mbits/s and 166.63 Mbits/s, respectively. When operating the TTRN0110G device at the RS FEC
OC-192/STM-64 rates, 622 Mbits/s and 155 Mbits/s should be interpreted as 669.33 Mbits/s and
167.33 Mbits/s, respectively.
Table 3. Ball Descriptions—622.08 Mbits/s and Related Signals
Ball
M10
N10
R10
P10
R9
P9
N8
P8
R7
R8
P7
N7
P6
R6
P5
R5
M5
N5
P4
R4
R2
R3
M3
N3
N2
P2
N1
P1
L1
M1
J1
K1
Symbol
*
D15P
D15N
D14P
D14N
D13P
D13N
D12P
D12N
D11P
D11N
D10P
D10N
D9P
D9N
D8P
D8N
D7P
D7N
D6P
D6N
D5P
D5N
D4P
D4N
D3P
D3N
D2P
D2N
D1P
D1N
D0P
D0N
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
indicates an internal pull-up resistor on this pin. I
d
indicates an internal pull-down resistor on this pin. I
t
= an
internal termination resistance of 50
to V
CCD
on this pin.
Type
I
Level
LVDS
Name/Description
Data Input (622 Mbits/s).
622 Mbits/s differential data input.
D15 is the most significant bit and is transmitted first on the
D10GP/N output.
Note:
This data rate will scale when operating at different rates.
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