參數(shù)資料
型號(hào)： TVP3010C
廠商： Texas Instruments, Inc.
英文描述： Video Interface Palette
中文描述： 視頻接口面板
文件頁(yè)數(shù)： 20/90頁(yè)
文件大?。?/td> 491K
代理商： TVP3010C
2–4
2.2
The color palette is addressed by an internal 8-bit address register for reading/writing data from/to the RAM.
This register is automatically incremented following a RAM transfer, allowing the entire palette to be
read/written with only one access of the address register. When the address register increments beyond
the last location in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM
are asynchronous to SCLK, VCLK, and dot clock but performed within one dot clock. Therefore, they do not
cause any noticeable disturbance on the display.
Color Palette
The color RAM is 24 bits wide for each location and 8 bits wide for each color. Since the MPU access is
8 bits wide, the color data stored in the palette is 8 bits even when the 6-bit mode is chosen
(8/6 = 0). If the 6-bit mode is chosen, the 2 MSBs of color data in the palette have the values previously
written. However, if they are read back in the 6-bit mode, the 2 MSBs are 0s to be compatible with IMSG176
and Bt176. The output multiplexer shifts the six LSB to the six MSB positions and fills the 2 LSBs with 0s
after the color palette. The multiplexer then feeds the data to the DAC. The test register and the CRC
calculation both take data after the output multiplexer, enabling total system verification. The color-palette
access is described in the following two sections, and it is fully compatible with IMSG176/8 and Bt476/8.
2.2.1
To load the color palette, the MPU must first write to the address register (write mode) with the address where
the modification is to start. This is then followed by three successive writes to the palette-holding register
with 8 bits of red, green, and blue data. After the blue write cycle, the three bytes of color data are
concatenated into a 24-bit word that is then written to the RAM location specified by the address register.
The address register then increments to the next location, which the MPU may modify by simply writing
another sequence of red, green, and blue data. A block of color values in consecutive locations may be
written to by writing the start address and performing continuous red, green, and blue write cycles until the
entire block has been written.
Writing to Color-Palette RAM
2.2.2
Reading from the palette is performed by writing to the address register (read mode) with the location to be
read. This then initiates a transfer from the palette RAM into the holding register, followed by an increment
of the address register. Three successive MPU reads from the holding register produce red, green, and blue
color data (6 or 8 bits depending on the 8/6 mode) for the specified location. Following the blue read-cycle,
the contents of the color-palette RAM at the address specified by the address register are copied into the
holding register and the address register is again incremented. As with writing to the palette, a block of color
values in consecutive locations may be read by writing the start address and performing continuous red,
green, and blue read-cycles until the entire block has been read. Since the color-palette RAM is dual ported,
the RAM may be read during active display without disturbing the video.
Reading From Color-Palette RAM
2.2.3
The palette page register appears as an 8-bit register on the extended register map (see Section 2.1). Its
purpose is to provide high-speed color changing by removing the need for palette reloading. When using
1, 2, or 4 bit-planes, the additional planes are provided from the page register. When using four bit-planes,
the pixel inputs specify the lower 4 bits of the palette address with the upper 4 bits specified from the page
register. This gives the user the capability of selecting from 16 palette pages with only one-chip access, thus
allowing all the screen colors to be changed at the line frequency. A bit-to-bit correspondence is used;
therefore, in the above configuration, page-register bits 7 through 4 map onto palette-address bits 7 through
4, respectively. This is illustrated in Table 2–3.
Palette Page Register
相關(guān)PDF資料
PDF描述
TVP3010M Video Interface Palette
TVP3020-175 Video Interface PALETTE(視頻接口調(diào)色器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3010M 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
TVP3020 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
TVP3020-135MDN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TVP3020-135PCE 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TVP3020-175MDN 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
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