參數(shù)資料
型號(hào)： TVP3010C
廠商： Texas Instruments, Inc.
英文描述： Video Interface Palette
中文描述： 視頻接口面板
文件頁(yè)數(shù)： 73/90頁(yè)
文件大?。?/td> 491K
代理商： TVP3010C
3–6
3.7 Timing Requirements (TVP3010C) (see Note 6)
TVP3010
-85
TVP3010
-110
TVP3010
-135
TVP3010
-170
UNIT
MIN
MAX
MIN
MAX
110
MIN
MAX
135
MIN
MAX
170
Dot clock frequency
CLK0 frequency for VGA
pass-through mode (see Note 7)
85
MHz
85
85
85
85
MHz
tc
Clock cycle time
TTL
11.8
9.1
7.4
7.1
ns
ECL
11.8
9.1
7.4
5.8
tsu1
Setup time, RS(0–3) valid before RD
or WR
↓
Hold time, RS(0–3) valid after RD or
WR
↓
Setup time, D(0–7)valid before WR
↑
Hold time, D(0–7)valid after WR
↑
Setup time, VGA(0–7) and VGABL
valid before CLK0
↑
(see Note 8)
Hold time, VGA(0–7) and VGABL
valid after CLK0
↑
(see Note 8)
Setup time, P(0–31) and PSEL valid
before LCLK
↑
(see Note 9)
Hold time, P(0–31) and PSEL valid
after LCLK
↑
(see Note 9)
Setup time, HSYNC, VSYNC, and
SYSBL valid before VCLK
↓
Hold time, HSYNC, VSYNC and
SYSBL valid after VCLK
↓
Pulse duration, RD or WR low
Pulse duration, RD or WR high
10
10
10
10
ns
th1
10
10
10
10
ns
tsu2
th2
35
0
35
0
35
0
35
0
ns
ns
tsu3
2
2
2
2
ns
th3
2
2
2
2
ns
tsu4
2
2
2
2
ns
th4
5
5
5
5
ns
tsu5
5
5
5
5
ns
th5
1
1
1
1
ns
tw1
tw2
50
30
4
50
30
3.5
50
30
3
50
30
3
ns
ns
t3
tw3
Pulse duration clock high
Pulse duration, clock high
TTL
ns
ECL
4
3
3
2.5
t4
tw4
Pulse duration clock low
Pulse duration, clock low
TTL
4
3.5
3
3
ns
ECL
4
3
3
2.5
tw5
Pulse duration, SFLAG high
(see Note 10)
30
30
30
30
ns
tw6
Pulse duration, SCLK high
(see Note 10)
NOTES:
6. TTL-input signals are 0 to 3 V with less than 3-ns rise/fall time between the 10% and 90% levels, unless
otherwise specified. ECL-input signals are VDD–1.8 V to VDD–0.8 V with less than 2-ns rise/fall time
between the 20% and 80% levels. For input and output signals, timing reference points are at the 10% and
90% signal levels. Analog-output loads are less than 10 pF. D(0–7) output loads are less than 50 pF. All
other output loads are less than 50 pF, unless otherwise specified.
7. In VGA mode, CLK0 minimum pulse duration for clock low should be greater than 4.8 ns. When VGA
switching is to be performed using self-clocked timing, the maximum pixel rate cannot exceed 50 MHz.
8. Reference to CLK0 input only.
9. RCLK is delayed from SCLK in such a way that when RCLK is connected to LCLK, the timing is essentially
the same as the TLC3407x family of parts.
10. This parameter applies when the split shift-register transfer (SSRT) function is enabled (see Section 2.15
for details).
15
55
15
55
15
55
15
55
ns
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