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參數(shù)資料
| 型號： | TVP3010C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 53/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TVP3010C |
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2–37
2.14 Video Control: Horizontal Sync, Vertical Sync, and Blank
For the high-resolution system modes, HSYNC and VSYNC are active-low pulses that are passed through
true/complement gates to the HSYNCOUT and VSYNCOUT outputs. The output polarities of HSYNCOUT
and VSYNCOUT can be programmed through the general control register. However, for the VGA mode, the
polarities required by the monitor are already provided at the feature connector where HSYNC and VSYNC
are sourced. Therefore, the palette passes them through to HSYNCOUT and VSYNCOUT without polarity
change. As described in Section 2.3 and Figures 2–2 through 2–5, the SYSBL, HSYNC and VSYNC inputs
are sampled and latched at the falling edge of VCLK in the system mode while VGABL, HSYNC, and VSYNC
are latched at the rising edge of CLK0 in the VGA mode. After SYSBL is sampled with VCLK, it is sampled
on the rising edge of the internal RCLK and passed to the dot-clock pipeline delay. When multiplexer control
register 2 bit 7 is set to 1 to activate the VGA port, the CLK0 and VGABL inputs are selected. Otherwise,
VCLK latches HSYNC, VSYNC, and SYSBL are selected.
HSYNC, VSYNC, and Blank (generated either from the system mode or VGA-mode video-control signals)
have internal pipeline delays so that the Sync and Blank signals align with the RGB data at the DAC outputs.
Due to the sample and latch-timing delay, it is possible to have active SCLKs after the selected blank input
becomes active. The relationship between VCLK and SCLK and the internal VCLK sample and latch delay
needs to be carefully reviewed and programmed (see Section 2.3 and Figures 2–2 and 2–3 for more details).
As shown in Figure 2–13, active HSYNC and VSYNC turns off the sync current source (after pipeline delay).
They are not qualified by the internal Blank signal. Therefore, to ensure proper operation, HSYNC and
VSYNC should be designed such that they are active only during Blank active time.
To alter the polarity of the HSYNCOUT and VSYNCOUT outputs, the MPU must set or clear the
corresponding bits in the general control register (see subsection 2.16.2). The polarity of these signals can
only be altered when not in VGA mode. These bits default to 0, which is an active-low output.
2.15 Split Shift Register Transfer VRAMs
Both the TVP3010C and the TVP3010M palettes have direct support for split-shift register transfer (SSRT)
VRAMs. In order to allow the VRAMs to perform a split-shift register transfer, an extra SCLK cycle must be
inserted during the Blank sequence. This is initiated when the SSRT enable bit 2 in the general control
register is set to 1 and a rising edge on the SFLAG input is detected. An SCLK pulse is generated within
20 ns of the rising edge of the SFLAG signal. A minimum 15-ns logic-high duration is provided to satisfy all
the –15 VRAM timing requirements. The rising edge of the SFLAG input triggers SCLK, but it needs to stay
high for a specified minimum duration. By controlling the SFLAG timing, the delay time from the rising edge
of VRAM TRG signal to SCLK can be satisfied. The relationship between SCLK, the SFLAG input, and
SYSBL is shown as follows:
SYSBL
SSRT Enable
(general-control
register-bit 2)
SFLAG Input
SCLK
Figure 2–16. Split Shift Register Transfer Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3010M | Video Interface Palette |
| TVP3020-175 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3020-135 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3010M | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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