參數(shù)資料
型號(hào)： TVP3010C
廠商： Texas Instruments, Inc.
英文描述： Video Interface Palette
中文描述： 視頻接口面板
文件頁(yè)數(shù)： 24/90頁(yè)
文件大小： 491K
代理商： TVP3010C
2–8
The output-clock-selection register is used to program the desired divided-down frequencies for the
reference/shift and video clocks.
2.3.2
The TVP3010C and the TVP3010M have two pixel-data latching modes, allowing for flexibility in the
frame-buffer interface timing. For the pixel port P(0–31), data is always latched on the rising edge of LCLK.
If auxiliary-control register (ACR) bit 3 is set to 1 (default), the internal circuitry is configured for self-clocked
mode. In this mode, the RCLK or SCLK output of the palette must be used as the timing reference to present
data to the pixel port P(0–31). In self-clocked mode, RCLK can be directly tied back to LCLK or LCLK can
be a delayed version of RCLK within the timing requirements of the VIP. The self-clocked mode of
frame-buffer latching is similar to the operation of the TLC3407X video-interface palette devices.
Frame-Buffer Clocking: Self-Clocked or Externally Clocked
The VIP internal Blank signal is generated from either VGABL or SYSBL, depending on whether the VGA
port is enabled (multiplexer control register 2 (MCR2) bit 7 = 1) or disabled (MCR2 bit 7 = 0). The rising edge
of CLK0 latches VGABL when the VGA port is enabled. The falling edge of VCLK is used to sample and
latch the SYSBL input when the VGA port is disabled. When the internal Blank signal becomes active, SCLK
is disabled as soon as possible. For example, if SCLK is high when the sampled SYSBL goes low, SCLK
is allowed to complete the clock cycle and return to the low state. SCLK then is held low until the sampled
SYSBL signal goes back high. At this time, SCLK is enabled to clock the first pixel data valid from VRAM.
The VIP video-blanking circuitry is designed with sufficient pipeline delay to allow the internal sampled
SYSBL and VGABL signals to align with the pipelined RGB data to the video DACs. The logic described
previously works in situations where the SCLK period is shorter than, equal to, or longer than the VCLK
period.
When in the self-clocked mode, the SCLK control timing is designed to interface directly with the external
VRAM. The shift register in the system VRAM is supposed to be updated during the blank active period.
When the SYSBL input is sampled high by the falling edge of VCLK, the VRAM shift clock (SCLK) is restarted
to clock the VRAM and enable the first group of pixel data to appear on the pixel bus as well as at the
TVP3010 pixel input port. The second SCLK causes the VRAM shift register to shift out the second group
of data. At the same time, LCLK latches the first group of pixel data into the VIP (see Figure 2–2 for a detailed
timing-diagram).
VCLK
In Phase
SYSBL
at Input Terminal
LD
Internal Delayed
LCLK = RCLK
Blank
(internal signal
before dot-clock
pipeline delay)
Pixel Data
at Input Terminal
SCLK
Latch Last Group
of Pixel Data
Latch First Group of Pixel Data
Latch Last Group
of Pixel Data
Last Group of Pixel Data
1st
Group
2nd
Group
3rd
Group
4th
Group
5th
Group
6th
Group
Figure 2–2. SCLK/VCLK Control Timing
(SSRT Disabled, RCLK/SCLK Frequency = VCLK Frequency)
The RCLK/SCLK phase relationship is designed so that timing specifications are satisfied for the case
where SCLK is driving a typical 2-MB VRAM load and RCLK is connected to LCLK. If an external buffer is
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PDF描述
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參數(shù)描述
TVP3010M 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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TVP3020-135MDN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TVP3020-135PCE 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TVP3020-175MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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