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參數(shù)資料
| 型號： | TVP3010C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 28/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TVP3010C |
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2–12
2.4
Both the TVP3010C and TVP3010M palettes offer a highly versatile multiplexing scheme as illustrated in
Tables 2–6 through 2–11. The multiplexing scheme allows the pixel bus to be programmed to 1, 2, 4, 8, 12,
16, 24, or 32 bits/pixel with pixel-bus widths ranging from 1 bit to 32 bits. The use of on-chip multiplexing
allows graphics systems to be designed that can support multiple-pixel depths and resolutions with no
hardware modification. It also allows the system to be configured to the amount of RAM available. For
example, when only 256K bytes of memory are available, an 800
×
600 mode with four bit-planes (4 bits
per pixel) could be implemented using an 8-bit-wide pixel bus. If at a later date another 256K bytes are added
to another 8 bits of the pixel bus, the user has the option of using eight bit-planes at the same resolution or
four bit-planes at a 1024
×
768 resolution. When a further 512K bytes are added to the remaining 16 bits
of the pixel bus, the user has the option of eight bit-planes at 1024
×
768 or four bit-planes at 1280
×
1024.
Each VIP can also be configured for direct-color or true-color operation. All of the above can be achieved
without any board-level hardware modification and without any increase in the speed of the pixel bus.
Multiplexing Scheme
Multiplexing of the pixel bus is controlled by and programmed through multiplexer control registers 1 and
2. For details of the multiplexer control register settings for each mode of operation, (see subsections 2.4.2
through 2.4.6).
2.4.1
Little-Endian and Big-Endian Data Format
The pixel bus on both the TVP3010C and TVP3010M supports both little-endian and big-endian data
formats for all pseudo-color, direct-color, and true-color modes of operation. The data-format select is
controlled by general control register-bit 3 (see subsection 2.16.2). When general control register (GCR)
bit 3 is cleared to 0 (default), then the format is set to little endian. When GCR bit 3 is set to 1, then the format
is set to big endian.
In a big-endian design, the external VRAM data-bus bits must be connected in reverse order to the VIP pixel
bus; i.e., D31 connected to P0, D0 connected to P31, etc. This ensures that the least-significant channel
always provides the first pixel to be displayed in the pseudo-color or true-color multiplexing modes. The
difference between little- and big-endian data formats and how they affect the pixel-bus operation is
discussed in detail in Appendix C.
2.4.2
VGA Pass-Through Mode
The TVP3010C and TVP3010M feature VGA pass-through mode.The VGA pass-through mode is used to
emulate the VGA modes of most personal computers. The advantage of this mode is that it can take data
presented on the feature connector of most VGA-compatible PC systems into the device on a separate bus,
thus requiring no external multiplexing. This feature is particularly useful in systems where the existing
graphics circuitry is on the motherboard. In this instance, it enables a drop-in graphics card to be
implemented that maintains compatibility with all existing software. This is accomplished by using the
on-board VGA circuitry but routing the emerging bit-plane data through the VIP. VGA pass-through is the
default mode at power up or reset.
Since this mode is designed with the feature connector philosophy, all data latching and control timing is
referenced to CLK0. When the VGA port is enabled (MCR2 bit 7 = 1), CLK0 is selected as the input clock
source independent of the input-clock-selection register. The VGA port always operates as in the externally
clocked mode of the pixel port P(0–31); it receives the VGA data [VGA(0–7)] and the VGA blank (VGABL),
both of which are referenced to an external clock (CLK0). CLK0 also latches the VGABL, HSYNC, and
VSYNC video-control signals when in the VGA pass-through mode. External signals on LCLK have no effect
on the VGA port since LCLK only latches data on the pixel port P(0–31).
VGA data pipeline delay is adjusted within the VIP depending on whether self- or externally clocked
frame-buffer interface timing is used (see subsection 2.3.2). When either device is programmed for
self-clocked timing, additional dot-clock pipeline delay is inserted into the internal VGA data path; this
permits the VGA and pixel-port data to remain synchronous when doing auxiliary window, port select, or
color-keyed switching (see Section 2.6). The additional VGA-pipeline delay accounts for the dot-
clock-to-RCLK pipeline delay within the palette.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3010M | Video Interface Palette |
| TVP3020-175 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3020-135 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3010M | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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