- 您現在的位置：買賣IC網 > PDF目錄385951 > TVP3010C (Texas Instruments, Inc.) Video Interface Palette PDF資料下載
參數資料
| 型號： | TVP3010C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數： | 27/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TVP3010C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
2–11
Externally clocked timing can be chosen for the pixel bus P(10–31) by clearing auxiliary control register bit 3
to 0. In externally clocked mode, the RCLK or SCLK output of the palette is not used as the timing reference
to present data to the pixel bus. Instead, pixel data is presented to the palette with a synchronous clock and
all palette timing is referenced to this clock. In this mode, the external clock should be connected to LCLK
and the selected clock input. (When the VGA port is enabled, the CLK0 input is selected independent of the
input-clock selection register.)
The externally clocked frame-buffer interface mode is intended for applications where windowed or
pixel-by-pixel switching between the VGA port and the pixel port is desired in non-VRAM-based graphics
systems. In such applications, the VGA port is enabled (multiplexer control register bit 7 set to 1) and the
appropriate direct-color mode is set in the multiplexer control register. The auxiliary-window, port-select,
and/or color-key switching functions are then configured and enabled to perform the desired switching. By
setting the frame-buffer interface to the externally clocked mode, the pixel port and VGA port timing and
pipeline delay are made the same. Also, since the VGA port is enabled, all video-control signal timing is
referenced to CLK0, utilizing the VGABL, HSYNC, and VSYNC inputs.
The externally clocked frame-buffer interface timing can also be used in non-VGA switching applications,
utilizing only the pixel port or only the VGA port. In either case, it is recommended that VGA video-control
signals be used (i.e., VGABL, HSYNC, VSYNC). In this way, all pixel data and video-control signals are
referenced to CLK0 and video blank and sync are aligned with pixel data.
NOTE:
When the pixel port is used in externally clocked mode (ACR3 = 0), RCLK must be
set to VCLK/1 (DOT/1) in the output-clock selection register and a 1:1 multiplexing
mode must be selected in the multiplexer control registers (see Table 2–6). The
external clock should be connected to the LCLK input as well as the selected clock
input. When the VGA port is also enabled (MCRB7 = 1), CLK0 is selected as the
input clock independent of the input-clock selection-register setting.
VGA switching can only be performed using a 1:1 multiplexing mode.
Overlay switching can only be performed using a 1:1 multiplexing mode when the
pixel port is set for externally clocked mode. When the pixel port is self-clocked, any
of the multiplex ratios may be used (see subsection 2.4.6).
When VGA switching is to be performed using externally clocked mode
(ACR3 = 0), the full VGA port frequency of 85 MHz may be utilized provided that
the VGA port and the pixel port are both synchronized to the CLK0 input clock.
If VGA switching is to be performed using self-clocked mode (ACR3 = 1), the
maximum pixel rate cannot exceed 50 MHz. This is because of internal delay from
the CLK0 input to the RCLK output. For external clocked timing, the LCLK input
needs to be enabled on terminal 73 (TVP3010C) or terminal L3 (TVP3010M) by
programming the configuration register bit 5 to 1.
VGA-data pipeline delay is adjusted within each VIP depending on whether self-
or externally clocked frame-buffer interface timing is used (see subsection 2.3.2 ).
If the VIP is programmed for self-clocked timing, three additional dot-clock pipeline
delays are inserted into the internal VGA-data path and into the internal blanking
signal. The additional pipeline delay accounts for the difference between VGABL
or SYSBL and the pixel-data inputs P(0–31) when used in the self- and externally
clocked modes. This is so the VGA and pixel-port data remain synchronous in time
when doing auxiliary window, port select, or color-keyed switching (see Section
2.6). When externally clocked timing is used, the VGA port and the pixel port are
already synchronous since both data and blanking are presented to the palette
during the same CLK0 clock cycle.
相關PDF資料 |
PDF描述 |
|---|---|
| TVP3010M | Video Interface Palette |
| TVP3020-175 | Video Interface PALETTE(視頻接口調色器) |
| TVP3020-135 | Video Interface PALETTE(視頻接口調色器) |
| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調色器) |
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調色器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TVP3010M | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
發(fā)布緊急采購，3分鐘左右您將得到回復。