![](http://datasheet.mmic.net.cn/390000/TVP3010C_datasheet_16839161/TVP3010C_85.png)
C–1
Appendix C
Little-Endian and Big-Endian Data Formats
It is commonly known in the computer industry that there are two different formats for memory configuration:
little-endian (Intel microprocessor-based format) and big-endian (Motorola microprocessor-based format).
When the Texas Instruments programmable pixel bus was introduced on the TLC34075 video-interface
palette, it allowed little-endian-based graphics-board manufacturers to design a single graphics board that
could be programmed to support multiple resolutions and pixel depths. The connection of the pixel bus from
the video RAM to the palette device was not a problem until big-endian-based customers desired the same
capability to program their graphics designs from 1 bit/pixel (bpp), 2 bpp, 4 bpp, 8 bpp, 12 bpp, 16 bpp,
24 bpp, to 32 bpp.
For this reason, the TVP3010C and the TVP3010M video-interface palettes support both little- and
big-endian data formats on its pixel-bus/frame-buffer interface. The device defaults to little-endian mode at
reset (general-control register-bit 3 set to 0) to be compatible with most PC-based systems. Big-endian
mode operation can be achieved by configuring the device to the big-endian mode (general-control
register-bit 3 set to 1) and externally reverse wiring the pixel bus from video RAM to the VIP on the graphics
board.
The differences between the big-endian and little-endian data formats are illustrated in Figure C–1. The
figure shows that the data fields representing the individual pixels in the big-endian format are in the reverse
order of the little-endian format. Since the VIP always shifts data from low-numbered data fields to
high-numbered data fields, external swapping of the pixel bus (i.e., D31 connected to P0, D0 connected to
P31) ensures that the pixels are displayed on the monitor in the correct sequence. However, swapping the
big-endian pixel bus causes the bits within each data field to be reversed (i.e., MSB to LSB instead of LSB
to MSB). When general-control register-bit 3 is set to 1, unique circuitry within the TVP3010 corrects the bit
sequence in each data field as it is shifted into the part. This correction is bit-plane independent and occurs
regardless of whether 8, 4, 2, or 1 bit/pixel are being used.
Both the TVP3010C and TVP3010M also support 12-, 16-, and 24-bit true-/direct-color for both little- and
big-endian data formats on the pixel bus. By using the same wiring for big-endian operation as described
above, all true-/direct-color modes are made available without hardware modification. Tables 2–8 through
2–11 give the true-/direct-color bit definitions for all modes. For example, when in one of the 16-bit true-color
modes (big endian), the first RGB data word to be displayed is located in bits 16–31 of VRAM. Swapping
the external pixel bus when designing the graphics board ensures the correct display sequence by causing
the first RGB word to appear at pixel-bus inputs P(0–15). However, the bit order within the word is reversed.
When general-control register-bit 3 is set to 1, the bit sequence is automatically corrected by circuitry within
the VIP.