參數(shù)資料
型號： TVP3010C
廠商： Texas Instruments, Inc.
英文描述： Video Interface Palette
中文描述： 視頻接口面板
文件頁數(shù)： 51/90頁
文件大小： 491K
代理商： TVP3010C
2–35
2.12 Frame-Buffer Interface
The TVP3010C as well as the TVP3010M provides three output clock signals and one input clock signal
for controlling the frame-buffer interface: SCLK, RCLK, LCLK, and VCLK. SCLK can be used to clock out
data from VRAM shift registers directly. Split shift register-transfer function is also supported. RCLK is
provided so that pixel-port P(0–31) data loading can be synchronized to the VRAM. LCLK rising edges latch
data presented on the pixel port, and VCLK clocks and synchronizes the video-control signals such as
HSYNC, VSYNC, SYSBL. Clocking of the frame-buffer interface (self-clocked and externally clocked
timing) is discussed in detail in subsection 2.3.2.
The 32-terminal interface allows many operational display modes as defined in Section 2.4 and Table 2–6.
The pixel-latching sequence is initiated by a rising edge on LCLK. For those multiplexed modes in which
multiple pixels are latched on one LCLK rising edge, the pixel clock shifts the pixels out starting with the
pixels that reside on the low-numbered pixel-port terminals. For example, in an 8-bit-per-pixel pseudo-color
mode with an 8:1 multiplex ratio, the pixel-display sequence is P(0–7), P(8–15), P(16–23), and P(24–31).
The VIP frame-buffer interface also supports little- and big-endian data formats on the pixel bus. This can
be controlled by general control register bit 3 (see subsections 2.4.1 and 2.16.2 and Appendix C for details
of operation).
2.13 Analog-Output Specifications
The DAC outputs are controlled by three current sources (only two for IOR and IOB) as shown in
Figure 2–13. The default condition is to have 0-IRE (Institute of Radio Engineers, predecessor to the IEEE)
difference between blank and black levels, which is shown in Figure 2–14. If a 7.5-IRE pedestal is desired,
it can be selected by setting bit 4 of the general control register. This video output is shown in Figure 2–15.
C (stray + load)
IOG
RL
～
15 pF
G0 – G7
Blank
Sync
(IOG Only)
AVDD
Figure 2–13. Equivalent Circuit of the Current Output (IOG)
A resistor (R
SET
) is needed between FS ADJUST and GND to control the magnitude of the full-scale video
signal. The IRE relationships in Figures 2–14 and 2–15 are maintained regardless of the full-scale output
current.
The relationship between R
SET
and the full-scale output current IOG is given in equation 3:
R
SET
(
) = K1
×
V
ref
(V)/IOG (mA)
(3)
The full-scale output current on IOR and IOB for a given R
SET
is given in equation 4:
IOR, IOB (mA) = K2
×
V
ref
(V)/R
SET
(
)
(4)
where K1 and K2 are defined as shown in Table 2–18.
相關(guān)PDF資料
PDF描述
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