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參數(shù)資料
| 型號(hào)： | TVP3010M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 21/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TVP3010M |
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2–5
NOTE:
The additional bits from the page register are inserted after the read mask.
The palette page register specifies the additional bit-planes for the overlay field in
direct-color modes with less than 8 bits per pixel overlay.
Table 2–3. Allocation of Palette Page Register Bits
NUMBER OF BIT PLANES
MSB
M
P7
PALETTE-ADDRESS BITS
LSB
8
M
M
M
M
M
M
M
4
P6
P5
P4
M
M
M
M
2
P7
P6
P5
P4
P3
P2
M
M
1
P7
P6
P5
P4
P3
P2
P1
M
M = bit from pixel port
Pn = n bit from page register
2.2.4
The read-mask register is an 8-bit register used to enable or disable a bit-plane from addressing the
color-palette RAM in the pseudo-color modes. Each palette address bit is logically ANDed with the
corresponding bit from the read mask register before going to the palette page register and addressing the
palette RAM.
Read Masking
In order to provide maximum flexibility to control palette data, the read mask operation is performed before
the addition of the page register bits. Therefore, care must be taken in those modes that have less than 8
bits per pixel of pseudo-color or overlay data. Be aware of the palette page register settings in these modes.
2.3
The TVP3010C and the TVP3010M VIP provide a maximum of five clock inputs. CLK0 is dedicated as a
TTL input. The other four clock inputs can be selected as either two differential ECL input or two extra TTL
inputs. The TTL inputs can be used for video rates up to 140 MHz. The dual-mode clock input (ECL/TTL)
is primarily an ECL input but can be used as TTL-compatible inputs if the input-clock selection register is
so programmed. The clock source used at power up is CLK0; an alternative source can be selected by
software during normal operation. This chosen clock input can be used unmodified as the dot clock
(representing pixel rate to the monitor). Alternatively, when the input-clock selection register is programmed
to use the internal frequency-doubler, the chosen clock source is used as a reference for multiplication. Each
device also allows for user programming of RCLK, SCLK and VCLK outputs (reference, shift and video
clocks) by using the output-clock selection register. The input-clock and output-clock selection registers are
located in the indirect register map (see Table 2–2).
Clock Selection and Output-Clock (SCLK, RCLK, and VCLK) Generation
The ECL inputs can be used as differential or single-ended inputs. When CLK1 or CLK3 is used as a
single-ended ECL input, CLK2 or CLK4 needs to be externally terminated to set the input common-mode
signal level. This can be done with a simple resistor divider, as is the case with fully differential ECL. Care
needs to be taken when choosing the resistor values to ensure that the dc level on CLK2 or CLK4 is in the
middle of the CLK1 or CLK3 ECL-input signal range.
2.3.1
Both VIP devices provide a user-programmable reference clock (RCLK), a shift clock (SCLK), and video
(VCLK) clock outputs that can be set as divisions of the dot clock. RCLK is a continuously-running reference
clock and is not disabled during the Blank signal. RCLK can be selected as divisions of 1, 2, 4, 8, 16, 32 or
64 of the
RCLK, SCLK, VCLK
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相關(guān)代理商/技術(shù)參數(shù) |
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| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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