參數(shù)資料
型號(hào): TVP3010M
廠商: Texas Instruments, Inc.
英文描述: Video Interface Palette
中文描述: 視頻接口面板
文件頁(yè)數(shù): 25/90頁(yè)
文件大?。?/td> 491K
代理商: TVP3010M
2–9
required on SCLK so that it can drive a larger load, a similar buffer can be placed on RCLK to match the
signal delay before connecting to LCLK. However, the delay from LCLK to RCLK cannot exceed one RCLK
period –7 ns, (see the timing-parameter specifications for more details).
When the VRAM split shift register operation is performed (see Figure 2–3 and Figure 2–4), the SCLK timing
is adjusted to work with the SFLAG input. Basically, the split shift register operation inserts an SCLK during
the blank period. This causes the first group of pixel data to appear at the pixel port during blank and allows
the first group of data to be displayed as soon as the palette comes out of blank. Figures 2–3 and 2–5 show
the case when the SSRT (split shift register transfer) function is enabled. When a rising edge occurs on the
SFLAG input, one SCLK with a minimum 15-ns pulse duration is generated after the specified delay. Since
this is designed to meet VRAM timing requirements, the SSRT-generated SCLK replaces the first SCLK in
the regular shift register transfer case as described above (see Section 2.15 for a detailed explanation of
the SSRT function).
VCLK
In Phase
SYSBL
at Input Terminal
LD
Internal Delayed
LCLK = RCLK
Blank
(internal signal
before dot-clock
pipeline delay)
Pixel Data
at Input Terminal
SCLK
Latch Last Group
of Pixel Data
Latch First Group of Pixel Data
Latch Last Group
of Pixel Data
SFLAG Input
Last
Group
2nd
Group
3rd
Group
4th
Group
5th
Group
6th
Group
1st Group of
Pixel Data
SCLK Between Split Shift-Register and Regular Shift-Register Transfer
Figure 2–3. SCLK/VCLK Control Timing
(SSRT Enabled, RCLK/SCLK Frequency = VCLK Frequency)
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