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參數(shù)資料
| 型號： | TVP3010M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 22/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TVP3010M |
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2–6
dot clock (see Table 2–4). It is provided as a clock reference and is typically connected back to the LCLK
input to latch pixel-port data. Since pixel-port data is latched on the rising edge of LCLK, the RCLK frequency
must be set as a function of the desired multiplexing ratio (that depends on the pixel-bus width and number
of bit-planes, see Section 2.4).
Table 2–4. Output-Clock Selection Register Format
OUTPUT-CLOCK SELECTION-REGISTER BITS (see Note 2)
6
5
4
3
0
0
0
FUNCTION (see Notes 2 3 4 and 5)
FUNCTION (see Notes 2, 3, 4, and 5)
2
x
1
x
0
x
VCLK/1 output ratio
0
0
1
x
x
x
VCLK/2 output ratio
0
1
0
x
x
x
VCLK/4 output ration
0
1
1
x
x
x
VCLK/8 output ratio
1
0
0
x
x
x
VCLK/16 output ratio
1
0
1
x
x
x
VCLK/32 output ratio
1
1
0
x
x
x
VCLK/64 output ratio
VCLK output held at logic 1
1
1
1
x
x
x
x
x
x
0
0
0
RCLK/1 output ratio (see Notes 2 and 5)
x
x
x
0
0
1
RCLK/2 output ratio (see Notes 2 and 5)
x
x
x
0
1
0
RCLK/4 output ratio (see Notes 2 and 5)
x
x
x
0
1
1
RCLK/8 output ratio (see Notes 2 and 5)
x
x
x
1
0
0
RCLK/16 output ratio (see Notes 2 and 5)
x
x
x
1
0
1
RCLK/32 output ratio (see Notes 2 and 5)
x
x
x
1
1
0
RCLK/64 output ratio (see Notes 2 and 5)
RCLK/64, SCLK output held at logic 0
0
x
x
x
1
1
0
0
x
x
x
1
1
1
RCLK, SCLK outputs held at logic 0
x
1
1
1
1
1
1
Clock counter reset (6)
These lines indicate the reset conditions as required for VGA pass-through.
NOTES:
2. Register bit 6 enables (1) and disables (default = 0) the SCLK output buffer. Register bit 7 is a don’t
care bit.
3. When the clocks are selected from one mode to the other, a minimum of 30 ns is needed before
the new clocks are stabilized and running.
4. When the output-clock-selection register is written with 3F (hex), the clock counter is reset,
RCLK = SCLK = 0, and VCLK = 1.
5. SCLK is the same as RCLK except that it is disabled during blank. When the RCLK divide ratio is
chosen, this sets the SCLK ratio as well.
SCLK is the same as RCLK but disabled during the Blank active period. SCLK is designed to be used as
the shift clock to interface directly with the VRAM. If SCLK is not used, the output can be switched off and
held low to protect against VRAM lockup due to invalid SCLK frequencies. The detailed SCLK control timing
is discussed in subsection 2.3.2.
VCLK is designed to be used as the timing reference by the graphics processor or other custom-designed
control logic to generate the graphics system control signals (SYSBL, HSYNC, and VSYNC). VCLK can be
selected as divisions of 1, 2, 4, 8, 16, 32, or 64 of the dot clock and can also be held at high (see Table 2–4).
The default setup is VCLK held at high since it is not used in VGA pass-through mode. Since these control
signals are sampled by VCLK, VCLK must be enabled for these to function properly.
Even though RCLK/SCLK and VCLK can be selected independently, there is still a relationship between
the two as discussed below. Many system considerations have been carefully covered in their design,
leaving maximum freedom to the user.
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| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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