- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385951 > TVP3010M (Texas Instruments, Inc.) Video Interface Palette PDF資料下載
參數(shù)資料
| 型號： | TVP3010M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 74/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TVP3010M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁當(dāng)前第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
3–7
3.8 Timing Requirements (TVP3010M) (see Note 6)
MIN
MAX
135
85
UNIT
MHz
MHz
Dot clock frequency
CLK0 frequency for VGA pass-through mode (see Note 7)
tc
Clock cycle time
TTL
7.4
ns
ECL
7.4
10
10
35
tsu1
th1
tsu2
th2
tsu3
th3
tsu4
th4
tsu5
th5
tw1
tw2
Setup time, RS(0–3) valid before RD or WR
↓
Hold time, RS(0–3) valid after RD or WR
↓
Setup time, D(0–7)valid before WR
↑
Hold time, D(0–7)valid after WR
↑
Setup time, VGA(0–7) and VGABL valid before CLK0
↑
(see Note 8)
Hold time, VGA(0–7) and VGABL valid after CLK0
↑
(see Note 8)
Setup time, P(0–31) and PSEL valid before LCLK
↑
(see Note 9)
Hold time, P(0–31) and PSEL valid after LCLK
↑
(see Note 9)
Setup time, HSYNC, VSYNC, and SYSBL valid before VCLK
↓
Hold time, HSYNC, VSYNC and SYSBL valid after VCLK
↓
Pulse duration, RD or WR low
Pulse duration, RD or WR high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
2
2
2
5
5
1
50
30
3
t3
tw3
Pulse duration clock high
Pulse duration, clock high
TTL
ns
ECL
3
t4
tw4
Pulse duration clock low
Pulse duration, clock low
TTL
3
ns
ECL
3
tw5
tw6
NOTES:
Pulse duration, SFLAG high (see Note 10)
Pulse duration, SCLK high (see Note 10)
30
15
ns
ns
55
6. TTL-input signals are 0 to 3 V with less than 3-ns rise/fall time between the 10% and 90% levels, unless
otherwise specified. ECL input signals are VDD–1.8 V to VDD–0.8 V with less than 2-ns rise/fall time
between the 20% and 80% levels. For input and output signals, timing reference points are at the 10% and
90% signal levels. Analog-output loads are less than 10 pF. D(0–7) output loads are less than 50 pF. All
other output loads are less than 50 pF, unless otherwise specified.
7. In VGA mode, CLK0 minimum pulse duration for clock low should be greater than 4.8 ns. When VGA
switching is to be performed using self-clocked timing, the maximum pixel rate cannot exceed 50 MHz.
8. Reference to CLK0 input only.
8. RCLK is delayed from SCLK in such a way that when RCLK is connected to LCLK, the timing is essentially
the same as the TLC3407x family of parts.
10. This parameter applies when the split shift-register transfer (SSRT) function is enabled (see Section 2.15
for details).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3020-175 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3020-135 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。