- 您現在的位置：買賣IC網 > PDF目錄385951 > TVP3010M (Texas Instruments, Inc.) Video Interface Palette PDF資料下載
參數資料
| 型號： | TVP3010M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數： | 23/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TVP3010M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
2–7
Internally, RCLK, SCLK, and VCLK are generated from a common clock counter that is counted at the rising
edge of the dot clock. Therefore, when VCLK is enabled, it is naturally in phase with RCLK and SCLK as
shown in Figure 2–1.
Normally, the video-control signal inputs HSYNC, VSYNC, and SYSBL are latched on the falling edge of
VCLK when in a non-VGA mode. When the configuration register is programmed for opposite VCLK polarity,
these video-control signals are latched on the rising edge of VCLK.
The internal clock counter is initialized any time the output-clock selection register is written with 3F (hex).
This provides a simple mechanism to synchronize multiple palettes or system devices by providing a known
phase relationship for the various system clocks. It is left up to the user to provide some means of disabling
the dot-clock input to the part while this reset is occurring if multiple parts are to be synchronized.
The reset default divide ratio for RCLK is 64:1 with SCLK held low and VCLK held at high. When choosing
certain video timing parameters, exercise caution if the selected RCLK frequency is less than the selected
VCLK frequency (see Appendix B for a more detailed discussion).
Dot Clock
VCLK
(dot clock/4 as an example)
RCLK = SCLK
(dot clock/2 as an example)
Figure 2–1. Dot Clock/VCLK/RCLK/SCLK Relationship
The input-clock-selection register selects the desired input-clock source. Table 2–5 details how to program
the various options.
Table 2–5. Input-Clock Selection Register
INPUT-CLOCK-SELECT REGISTER
(HEX) (see Note 6)
FUNCTION (see Note 7)
00
Select CLK0 as TTL-clock source
01
Select CLK1 as TTL-clock source
02
Select CLK2 as TTL-clock source
03
04
06
07
Select CLK3 as TTL-clock source
Select CLK4 as TTL-clock source
Select CLK3/CLK4 as ECL-clock source up to 140 MHz
Select CLK1/CLK2 as ECL-clock source up to device limit
10
Select CLK0 as doubled TTL-clock source
11
Select CLK1 as doubled TTL-clock source
12
Select CLK2 as doubled TTL-clock source
13
Select CLK3 as doubled TTL-clock source
14
Select CLK4 as doubled TTL-clock source
16
Select CLK3/CLK4 as doubled ECL-clock source
17
Select CLK1/CLK2 as doubled ECL-clock source
CLK0 is chosen at reset as required for VGA pass-through.
NOTES:
6. Register bits 3 and 7 are don’t-care bits.
7. Register bits 5 and 6 are reserved.
8. When the clocks are selected from one input clock source to another, a minimum of 30 ns is needed before
the new clocks are stabilized and running.
相關PDF資料 |
PDF描述 |
|---|---|
| TVP3020-175 | Video Interface PALETTE(視頻接口調色器) |
| TVP3020-135 | Video Interface PALETTE(視頻接口調色器) |
| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調色器) |
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調色器) |
| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調色器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
發(fā)布緊急采購，3分鐘左右您將得到回復。