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參數(shù)資料
| 型號： | TVP3010M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 77/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TVP3010M |
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3–10
3.10 Switching Characteristics for TVP3010M, Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature (see Figures 3-1
to 3-3)
PARAMETER
MIN
TYP
MAX
UNIT
SCLK frequency (CL
≤
15 pF) (see Note 11)
SCLK frequency (CL
≤
60 pF) (see Note 11)
RCLK, VCLK frequency (see Note 11)
85
MHz
85
MHz
85
MHz
ten
tdis
tv
tPLH
td1
Enable time, RD low to D(0–7) valid
40
ns
Disable time, RD high to D(0–7) disabled
17
ns
Valid time, D(0–7) valid after RD high
Propagation delay, SFLAG
↑
to SCLK high (see Notes 11 and 12)
Delay time, RD low to D(0–7) starting to turn on
5
ns
0
20
ns
5
ns
td2
Delay time, selected input clock high/low to dot clock (internal signal)
high/low
7
ns
td3
td4
td5
td6
Delay time, SCLK high/low to RCLK high/low (see Note 13)
0
2
6
ns
Delay time, VCLK high/low to RCLK high/low (see Note 13)
0
3
6
ns
Delay time, RCLK high/low from dot clock high/low (internal signal)
7
ns
Delay time, LCLK from RCLK
tRCLK–7
ns
td7
Delay time, dot clock high to IOR/IOG/IOB active (analog output
delay time) (seeNote14)
4
ns
td8
td9
tr
Analog output settling time(seeNote 15)
6
ns
Delay time, dot clock high to HSYNCOUT and VSYNCOUT valid
9
ns
Analog output rise time (see Note 16)
2
ns
Analog output skew
0
4
ns
NOTES: 11. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and
90% levels is less than 4 ns (typical 3 ns). RCLK and VCLK can drive output capacitive loads up to 15 pF,
with worst-case transition times between 10% and 90% levels less than 4 ns (typical 3 ns).
12. This parameter applies when the split-shift register transfer (SSRT) function is enabled (see Section 2.15
for details).
13. The SCLK and VCLK delay time to RCLK depends on the load that the signals drive. This parameter is
measured with an RCLK to VCLK ratio of 1:1, a VCLK = RCLK load of 15 pF, and an SCLK load of 60 pF.
14. Measured from the 90% point of the rising edge of the internal dot-clock signal to 50% of the full-scale
transition
15. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
±
1 LSB (settling time does not include clock and data feedthrough)
16. Measured between 10% and 90% of the full-scale transition
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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