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D–1
Appendix D
Examples: Register Settings
Table D–1. 8-Bit/Pixel Pseudo-Color (32-Bit Pixel Bus, 4:1)
Self-Clocked, LCLK and RCLK Enabled
REGISTER
INDEX
(HEX)
SETTING
(HEX)
DESCRIPTION
Input-Clock Selection
1A
xx
Any clock can be chosen
Output-Clock Selection
1B
52
RCLK = SCLK = /4, VCLK = /4 (VCLK could be different)
General Control
1D
20
Default settings
Auxiliary Control
29
09
Default settings, self-clocked, palette graphics, no zoom
Color-Key Control
38
10
Default settings, pointing to palette graphics
Multiplexer-Control Register 1
18
80
Pseudo-color
Multiplexer-Control Register 2
19
1B
8 bpp, 4:1, 32-bit pixel bus width
Configuration Register
1E
30
Enable LCLK and RCLK
Table D–2. 24-Bit True Color (32-Bit Pixel Bus, 1:1) Self-Clocked, RCLK = LCLK Internal
REGISTER
INDEX
(HEX)
SETTING
(HEX)
DESCRIPTION
Input-Clock Selection
1A
xx
Any clock can be chosen
Output-Clock Selection
1B
40
RCLK = SCLK = /1, VCLK = /1 (VCLK could be different)
General Control
1D
20
Default settings
Auxiliary Control
29
09
Default settings, self-clocked, palette graphics, no zoom
Color-Key Control
38
10
Default settings, pointing to palette graphics
Multiplexer-Control Register 1
18
46
24-bit true color
Multiplexer-Control Register 2
19
03
24-bit true color, 32-bit pixel-bus width
Configuration Register
1E
00
Default setting, RCLK internally connected to LCLK
Table D–3. 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Self-Clocked, No Overlay
REGISTER
INDEX
(HEX)
SETTING
(HEX)
DESCRIPTION
Input-Clock Selection
1A
xx
Any clock can be chosen
Output-Clock Selection
1B
40
RCLK = SCLK = /1, VCLK = /1 (VCLK could be different)
General Control
1D
20
Default settings
Auxiliary Control
29
08
Self-clocked, no window, nonpalette graphics, no zoom
Color-Key Control
38
00
Disabled, pointing to nonpalette graphics
Multiplexer-Control Register 1
18
06
24-bit direct color
Multiplexer-Control Register 2
19
1B
24-bit direct color, 32-bit pixel bus width